ST STM32F10 Series Application Note Download Page 16 | Manualshive

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Boot configuration

AN2586 - Application note

3.3

Embedded Boot Loader mode

The Embedded Boot Loader mode is used to reprogram the Flash memory using one of the
serial interfaces (typically a UART). This program is located in the system memory and is
programmed by ST during production.

For details, refer to the STM32F10xxx Flash programming manual, PM0042, available from
the STMicroelectronics website, www.st.com.

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Summary of Contents for STM32F10 Series

Page 1: ...pment board features such as the power supply the clock management the reset control the boot mode settings and the debug management It shows how to use the STM32F10xxx product family and describes th...

Page 2: ...xternal source HSE bypass 12 2 1 2 External crystal ceramic resonator HSE crystal 12 2 2 LSE OSC clock 13 2 2 1 External source LSE bypass 13 2 2 2 External crystal ceramic resonator LSE crystal 13 2...

Page 3: ...Contents 3 23 4 3 4 SWJ debug port connection with Standard JTAG connector 19 5 Reference design 20 5 1 Main 20 5 1 1 Clock 20 5 1 2 Reset 20 5 1 3 Boot mode 20 5 2 SWJ interface 20 5 3 Power supply 2...

Page 4: ...List of tables AN2586 Application note 4 23 List of tables Table 1 Boot modes 15 Table 2 Debug port pin assignment 18 Table 3 SWJ I O pin availability 18 Table 4 Document revision history 22...

Page 5: ...esholds 9 Figure 5 Reset circuit 10 Figure 6 Clock overview 11 Figure 7 External clock 12 Figure 8 Crystal ceramic resonators 12 Figure 9 External clock 13 Figure 10 Crystal ceramic resonators 13 Figu...

Page 6: ...and shielded from noise on the PCB the ADC voltage supply input is available on a separate VDDA pin an isolated supply ground connection is provided on the VSSA pin When available depending on packag...

Page 7: ...p mode the regulator supplies low power to the 1 8 V domain preserving the contents of the registers and SRAM in Standby mode the regulator is powered off The contents of the registers and SRAM are lo...

Page 8: ...oper operation starting from 2 V The device remains in the Reset mode as long as VDD is below a specified threshold VPOR PDR without the need for an external reset circuit For more details concerning...

Page 9: ...n VDD rises above the PVD threshold depending on the EXTI Line16 rising falling edge configuration As an example the service routine can perform emergency shutdown tasks Figure 4 PVD thresholds 1 3 3...

Page 10: ...Application note 10 23 Figure 5 Reset circuit RON VDD Filter 0 1 F External reset circuit NRST System nreset WWDG reset IWDG reset POR PDR reset Software reset Low power management reset Pulse genera...

Page 11: ...peed internal clock signal LSE low speed external clock signal HSE OSC 4 16 MHz OSC_IN OSC_OUT OSC32_IN OS32_OUT LSE OSC 32 768 kHz LSI RC 32 kHz PLL x2 x3 x4 PLLMUL MCO Clock Output Main PLLXTPRE x16...

Page 12: ...configuration is shown in Figure 8 The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilizat...

Page 13: ...low power but highly accurate clock source to the real time clock peripheral RTC for clock calendar or other timing functions The resonator and the load capacitors have to be connected as close as pos...

Page 14: ...ock security system interrupt CSSI allowing the MCU to perform rescue operations The CSSI is linked to the Cortex M3 NMI non maskable interrupt exception vector If the HSE oscillator is used directly...

Page 15: ...dby mode Even when aliased in the boot memory space the related memory Flash memory or SRAM is still accessible at its original memory space After this startup delay has elapsed the CPU starts code ex...

Page 16: ...de is used to reprogram the Flash memory using one of the serial interfaces typically a UART This program is located in the system memory and is programmed by ST during production For details refer to...

Page 17: ...pin interface and a SW DP 2 pin interface The JTAG debug port JTAG DP provides a 5 pin standard JTAG interface to the AHP AP port The serial wire debug port SW DP provides a 2 pin clock data interface...

Page 18: ...w st com 4 3 3 Internal pull up and pull down on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip flops to control the debug mode features Special care must...

Page 19: ...ware can then use these I Os as standard GPIOs Note The JTAG IEEE standard recommends to add pull up resistors on TDI TMS and nTRST but there is no special recommendation for TCK However for the STM32...

Page 20: ...eset The reset signal in Figure 14 is active low The reset sources include Reset button B1 Debugging tools via the connector CN1 Refer to Section 1 3 Reset power supply supervisor on page 8 5 1 3 Boot...

Page 21: ...1_TX TIM1_CH2 68 PA10 USART1_RX TIM1_CH3 69 PA11 USART1_CTS CANRX USBDM 2 TIM1_CH4 70 PA12 USART1_RTS CANTX USBDP 2 TIM1_ETR 71 PA13 JTMS SWDAT 72 Not connected 73 PA14 JTCK SWCLK 76 PA15 JTDI 77 PB3...

Page 22: ...Revision history AN2586 Application note 22 23 6 Revision history Table 4 Document revision history Date Revision Changes 12 Jul 2007 1 Initial release...

Page 23: ...IED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT...

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