ST STA380BW, Manual

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STA380BW Register description: Sound Terminal compatibility
To make the STA380BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock which means that:

the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on
the settings in
Table 29 on page 58

the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA380BW will immediately mute the I
2
S PCM data out (provided to the processing block)
and it will freeze any active processing task.
To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any
audio streams flowing into the STA380BW data path before the desynchronization event
Table 104. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
1100 1 I
2
S 15-bit data
1110 1 Left/right-justified 16-bit data
48 * fs
0100 1 I
2
S 23-bit data
0100 1 I
2
S 20-bit data
1000 1 I
2
S 18-bit data
1100 1 LSB first I
2
S 16-bit data
0001 1 Left-justified 24-bit data
0101 1 Left-justified 20-bit data
1001 1 Left-justified 18-bit data
1101 1 Left-justified 16-bit data
0010 1 Right-justified 24-bit data
0110 1 Right-justified 20-bit data
1010 1 Right-justified 18-bit data
1110 1 Right-justified 16-bit data
64 * fs
0000 1 I
2
S 24-bit data
0100 1 I
2
S 20-bit data
1000 1 I
2
S 18-bit data
1100 1 LSB first I
2
S 16-bit data
0001 1 Left-justified 24-bit data
0101 1 Left-justified 20-bit data
1001 1 Left-justified 18-bit data
1101 1 Left-justified 16-bit data
0010 1 Right-justified 24-bit data
0110 1 Right-justified 20-bit data
1010 1 Right-justified 18-bit data
1110 1 Right-justified 16-bit data
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