Register description: New Map
STA380BW
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DocID024543 Rev 1
6.12.2
Interpolation ratio selection
The STA380BW has variable interpolation (oversampling) settings such that internal
processing and FFX output rates remain consistent. The first processing block interpolates
by either 3 times (
Table 83: PLL register 0x56 bits
D0), 2 times or 1 time (pass-through) or
provides a 2-times downsample. The oversampling ratio of this interpolation is determined
by the IR bits.
6.12.3
Fault-detect recovery bypass
The on-chip STA380BW power output block provides feedback to the digital controller using
inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block
attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which
directs the power output block to begin recovery), holds it at 0 for period of time in the range
of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC
registers 0x3C-0x3D), then toggles it back to 1. This sequence is repeated as long as the
fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
Table 28. Internal interpolation ratio
Bit
R/W
RST
Name
Description
4:3
R/W
00
IR [1:0]
Selects internal interpolation ratio based on input I
2
S
sampling frequency
Table 29. IR bit settings as a function of the input sampling rate
Input sampling rate fs (kHz)
IR
1st stage interpolation ratio
32
00
2-times oversampling
44.1
00
2-times oversampling
48
00
2-times oversampling
88.2
01
Pass-through
96
01
Pass-through
176.4
10
2-times downsampling
192
10
2-times downsampling
Table 30. Fault-detect recovery bypass
Bit
R/W
RST
Name
Description
7
R/W
0
FDRB
0: fault-detect recovery enabled
1: fault-detect recovery disabled
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