ST STA380BW, Manual, Page: 59 / 162

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STA380BW Register description: New Map
6.13 Configuration register B (addr 0x12)
6.13.1 Serial data interface
The STA380BW audio serial input was designed to interface with standard digital audio
components and to accept a number of serial data formats. The STA380BW always acts as
the slave when receiving audio input from standard digital audio components. Serial data for
two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and
serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I
2
S, MSB-first. Available formats are shown in the tables
that follow.
6.13.2 Serial data first bit
D7 D6 D5 D4 D3 D2 D1 D0
C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0
1 0 0 0 0 0 0 0
Table 31. Serial data first bit
SAIFB Format
0 MSB-first
1 LSB-first
Table 32. Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
0000 0 I
2
S 15-bit data
0001 0 Left/right-justified 16-bit data
48 * fs
0000 0 I
2
S 16- to 23-bit data
0001 0 Left-justified 16- to 24-bit data
0010 0 Right-justified 24-bit data
0110 0 Right-justified 20-bit data
1010 0 Right-justified 18-bit data
1110 0 Right-justified 16-bit data
64 * fs
0000 0 I
2
S 16- to 24-bit data
0001 0 Left-justified 16- to 24-bit data
0010 0 Right-justified 24-bit data
0110 0 Right-justified 20-bit data
1010 0 Right-justified 18-bit data
1110 0 Right-justified 16-bit data
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