Register description: Sound Terminal compatibility
STA380BW
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DocID024543 Rev 1
Figure 45. Alternate function for INTLINE pin
7.22.5
Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
As per
, the assertion of PWDN activates a counter that, by default, after 13
million clock cycles puts the power bridge in tristate mode, independently from the fade-out
time. Using these registers it is possible to program this counter according to the following
table.
7.22.6
Short-circuit check enable bit (address 0x4C, bit D0)
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section
for more details.
Y
N
‘0 ’
L P D
“is th e d evice in p ow erd o w n ?”
0
1
LP D P
0
1
L P D E
P o w er B rid ge Fau lt
IN T L IN E
Table 166. PNDLSL bits configuration
PNDLSL[2]
PNDLSL[1]
PNDLSL[2]
Fade-out time
0
0
0
Default time (13M PLL clock cycles)
0
0
1
Default time divided by 2
0
1
0
Default time divided by 4
0
1
1
Default time divided by 8
1
0
0
Default time divided by 16
1
0
1
Default time divided by 32
1
1
0
Default time divided by 64
1
1
1
Default time divided by 128
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