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STA380BW
Register description: Sound Terminal compatibility
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the EAPD/FFX4B output pin when OCFG = 10.
7.7
Volume control registers (addr 0x06 - 0x0A)
7.7.1
Mute/line output configuration register
Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always channel 1 and 2 inputs.
D7
D6
D5
D4
D3
D2
D1
D0
LOC1
LOC0
Reserved
BQBALL
C3M
C2M
C1M
MMUTE
0
0
0
0
0
0
0
0
Table 126. Line output configuration
LOC[1:0]
Line output configuration
00
Line output fixed - no volume, no EQ
01
Line output variable - CH3 volume effects line output, no EQ
10
Line output variable with EQ - CH3 volume effects line output
11
Reserved
Bit
R/W
RST
Name
Description
4
R/W
0
BQBALL
Global biquad bypass
0: Biquad filters active
1: All the biquad filters are bypassed (pass-through)
Table 127. Mute configuration
Bit
R/W
RST
Name
Description
3
R/W
0
C3M
Channel 3 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 3 in hardware mute
2
R/W
0
C2M
Channel 2 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 2 in hardware mute
1
R/W
0
C1M
Channel 1 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 1 in hardware mute
0
R/W
0
MMUTE
Master mute
0 - Normal operation
1 - All channels are in mute condition
Obsolete Product(s) - Obsolete Product(s)
