
FCCU input #
Source
Failure description
Error reaction path
79
TCU
Test circuitry group 2 activation
Not testable
80
TCU
Test circuitry group 3 activation
Not testable
81
TCU
Test circuitry group 4 activation
Not testable
84
PLATFORM/CORE
Safety Core_2 exception (machine check exception)
Testable
89
PLATFORM/PBRIDGE
PBRIDGE_1 e2eEDC error
Not testable
91
PLATFORM/PBRIDGE
PBRIDGE_2 e2eEDC error
Not testable
94
MC_RGM
Safe mode entry indication
Not testable
95
COMPENSATION CELLS Pad compensation deactivation
Not testable
96
GLUE LOGIC
Error input pin (from the external world)
Testable
1. Aggregate of RAM correctable error overflow flag, RAM uncorrectable error overflow flag, RAM error buffer overflow flag.
2. Aggregate of peripheral RAM correctable error overflow flag, peripheral RAM uncorrectable error overflow flag, peripheral
RAM error buffer overflow flag.
3. FHH or FLL event for CMU_0.
4. FHH or FLL event from CMU_1, CMU_2, CMU_3, CMU_11, CMU_14.
5. FHH or FLL event from CMU_6, CMU_12.
Before the safety application starts, the user shall configure a proper reaction for each FCCU failure input
source. See “FCCU registers reset values” paragraph in SPC582Bx Reference Manual for the device default
configuration.
Possible reactions to a failure are:
•
Internal reactions:
Note:
The user can configure separately the internal reaction for each FCCU input.
–
No reset reaction
–
IRQ
–
Short functional reset
–
Long functional reset
–
NMI
•
External reaction:
–
Error out (EOUT) signaling.
The FCCU controls EOUT pins that signal the status of the MCU without any core intervention.
A dedicated module called FOSU monitors the integrity of the FCCU. The FOSU triggers a destructive reset if its
internal counter reaches a timeout before the FCCU takes a reaction to an incoming – and enabled – fault.
Note:
There is a 'do nothing' FOSU input coming from the FCCU that indicates that the FCCU is programmed for no
reaction.
The FOSU does not require any configuration done by the user. A functional reset has no impact on the FCCU.
AN5752
Overview
AN5752
-
Rev 1
page 4/35