The user can inject this fault by:
1.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
2.
Enabling the customer programmable read voltage and reference detection (FLASH_0_UT0[CPR] = 0x1);
3.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
4.
Accessing the customer programmable detection area in the UTEST block (address 0x0040_02E0 to
0x0040_02FF). The user can clear the fault by:
5.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
6.
Disabling the customer programmable read voltage and reference detection (FLASH_0_UT0[CPR] = 0x0);
7.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
8.
Clear the relevant Flash error flag (FLASH_0_MCR[RRE]);
9.
Clear the relevant FCCU_RF_S1[RFS31] bit. The FCCU error reaction path is verified if the
FCCU_RF_S1[RFS31] status bit is set after step (4).
3.7.3
EDC after ECC for Flash array (fault #64)
The EDC after ECC logic inside the PFLASHC detects a hardware fault in the ECC logic resulting in a corrupted
ECC correction for the Flash array and the PFLASHC forwards this fault to the FCCU.
The user can inject this fault by:
1.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
2.
Enabling the customer programmable EDC after ECC detection (FLASH_0_UT0[CPE] = 0x1);
3.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
4.
Accessing the customer programmable detection area in the UTEST block (address 0x0040_02E0 to
0x0040_02FF). The user can clear the fault by:
5.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
6.
Disabling the customer programmable EDC after ECC detection (FLASH_0_UT0[CPE] = 0x0);
7.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
8.
Clear the relevant FLASH error flag (FLASH_0_MCR[EEE]);
9.
Clear the relevant FCCU_RF_S2[RFS0] bit. The FCCU error reaction path is verified if the
FCCU_RF_S2[RFS0] status bit is set after step (4).
3.7.4
EDC after ECC for Flash controller (fault #65)
The EDC after ECC logic inside the PFLASHC detects a hardware fault in the ECC logic resulting in a corrupted
ECC correction for the Flash controller and the PFLASHC forwards this fault to the FCCU.
The user cannot inject this fault.
3.7.5
Flash encoding error (fault #66)
The PFLASHC detects faults resulting in a corrupted Flash memory access and it forwards this fault to FCCU.
The user can inject this fault by:
1.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
2.
Enabling the customer programmable address encode detection (FLASH_0_UT0[CPA] = 0x1);
3.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
4.
Accessing the customer programmable detection area in the UTEST block (address 0x0040_02E0 to
0x0040_02FF). The user can clear the fault by:
5.
Enabling the user test (FLASH_0_UT0[UTE] = 0x1);
6.
Disabling the customer programmable address encode detection (FLASH_0_UT0[CPA] = 0x0);
7.
Disabling the user test (FLASH_0_UT0[UTE] = 0x0);
8.
Clear the relevant FLASH error flag (FLASH_0_MCR[AEE]);
9.
Clear the relevant FCCU_RF_S2[RFS2] bit. The FCCU error reaction path is verified if the
FCCU_RF_S2[RFS2] status bit is set after step (4).
AN5752
Flash/PFLASHC faults
AN5752
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Rev 1
page 13/35