ST SPC582B Series, Application Note, Page: 18 / 35

3.11.2 SMPU XBAR 1 monitor correctly refuses an access (fault #34)
In case of a memory access not mapped to any region descriptor or with insufficient rights, it terminates with
an access error response and the HW monitors inside the SMPU detects this event and forwards this fault to
the FCCU. The user can inject this fault by a SW procedure that accesses a memory address not allowed by
the SMPU. A data storage interrupt (IVOR2) must be handled. The FCCU error reaction path is verified if the
FCCU_RF_S1[RFS2] status bit is set.
3.12 Core_2 faults
3.12.1 Core_2 I-bus ECC error (fault #12)
Instruction and data busses between XBAR and the Core_2 are protected by e2e_ECC.
In case an ECC error is detected on Core_2 instruction bus, the e2e_ECC forwards this fault to the FCCU.
The user cannot inject this fault.
3.12.2 Core_2 D-bus ECC error (fault #13)
Instruction and data busses between XBAR and the Core_2 are protected by e2e_ECC.
In case of an ECC error is detected on Core_2 data bus, the e2e_ECC forwards this fault to the FCCU.
The user cannot inject this fault.
3.12.3 Safety Core_2 exception (machine check exception) (fault #84)
When the Core_2 runs into a machine check condition, the Core_2 forwards this fault to the FCCU.
The user can inject this fault by a SW procedure that accesses to a not existing address. The machine check
interrupt (IVOR1) must be handled. The FCCU error reaction path is verified if the FCCU_RF_S2[RFS20] status
bit is set.
3.13 PLLDIG faults
The SPC582Bx embeds a dual PLL system which provides separate system and peripheral clocks.
For further details on dual PLL, refer to the device SPC582Bx reference manual
RM0403 .
Figure 14. PLL DIG faults
RGM
Error out
Reset request
reset
PLL0
Fault #49
FCCU
INTC
Interrupt request
Interrupt
PLL1
Fault #50
3.13.1 PLL0 loss of lock error (fault #49)
A built-in mechanism can detect a loss of lock for the PLL0. The relevant PLLDIG forwards this fault
to the FCCU. The user can inject this fault by a SW procedure that enables the loss of lock interrupt
(PLLDIG_PLL0CR[LOLIE] = 1) and changes on-the-fly the PLL configuration (for example, change on-the-fly the
value of the PLLDIG_PLL0DV[PREDIV] field) that generates a temporary loss of lock. The FCCU error reaction
path is verified if the FCCU_RF_S1[RFS17] and the PLLDIG_PLL0SR[LOLF] status bits are set. The user must
restore on-the-fly the PLL configuration, wait for the new lock and clear PLLDIG_PLL0SR[LOLF] status bit before
clearing the relevant FCCU_RF_S1[RFS17] bit.
AN5752
Core_2 faults
AN5752 - Rev 1
page 18/35