3.5 Status Model
3 – 25
3.5
Status Model
The SIM960 status registers follow the hierarchical IEEE–488.2 for-
mat. A block diagram of the status register array is given in Figure 3.1.
7
X
5
4
3
2
1
0
CESB
MSS
ESB
IDLE
undef
undef
ADSB
INSB
7
6
5
4
3
2
1
0
Status Byte
SB
SRE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OPC: Operation Complete
INP: Input Buffer Error
DDE: Device Error
EXE: Execution Error
CME: Command Error
URQ: User Request
PON: Power On
QYE: Query Error
ESR
ESE
Standard Event Status
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PARITY: Parity Error
FRAME: Framing Error
HWOVRN: Hardware Overrun
OVR: Input Buffer Overrun
RTSH: RTS Halted
CTSH: CTS Halted
DCAS: Device Clear
NOISE: Noise Error
CESR
CESE
Communication Error Status
-STATUS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ADSETP: Setpoint Mon
ADMEAS: Measure Mon
ADOUT: Output Mon
undef
undef
undef
undef
ADERR: Error Signal Mon
ADSR
ADSE
Analog to Digital Status
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OVLD
ULIMIT
ANTIWIND
RSTOP
undef
undef
undef
LLIMIT
Instrument Status
INSE
INSR
7
6
5
4
3
2
1
0
INCR
Figure 3.1: Status Register Model for the SIM960 Analog PID Con-
troller.
There are three categories of registers in the SIM960 status model:
Condition Registers : These read-only registers correspond to the real-time condi-
tion of some underlying physical property being monitored.
Queries return the latest value of the property, and have no
other e
ff
ect. Condition register names end with
CR
.
Event Registers : These read-only registers record the occurrence of defined
events. If the event occurs, the corresponding bit is set to
1. Upon querying an event register, any set bits within it are
cleared These are sometimes known as “sticky bits,” since once
set, a bit can only be cleared by reading its value. Event register
names end with
SR
.
Enable Registers : These read
/
write registers define a bitwise mask for their cor-
responding event register. If any bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with
SE
.
SIM960 Analog PID Controller
