PulseBlaster
Board Architecture
Block Diagram
Figure 1 presents the general architecture of the PulseBlaster system. The major building blocks
are the SRAM memory (both internal and external
to the processor), the microcontroller (uPC), the
integrated bus controller (IBC), the counter, and the output buffers. The entire logic design, excluding
output buffers, is contained on a single silicon chip, making it a System-on-a-Chip design. User control
to the system is provided through the IBC over the peripheral component interconnect (PCI) bus.
Figure 1:
PulseBlaster board architecture. The clock oscillator signal is derived from an on-chip PLL circuit
typically using a 50 MHz on-board reference clock.
Key Features
Output Signals
The PulseBlaster PB24 models allow for 24 digital output signal lines. Sixteen output lines are
routed to a DB25 bracket-mounted connector. On the SP17 and the PCIe boards, all 24 output lines
are for routed to IDCs. The PB12 models allow for 12 digital output signal lines (bits 0 to 11 as
). The individually controlled digital output lines comply with the
transistor-transistor logic (TTL) levels’ standard, and are capable of delivering up to
±
25 mA per
bit/channel. The number of output channels and current output are dependent on the board and
. If the load being driven is less than 132 Ohms, the
1
SP46 boards do not have external SRAM.
2021/03/22
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PCI Bus
PCI Bus
