PulseBlaster
Appendix I: Controlling the PulseBlaster with SpinAPI
Introduction
This section provides detailed descriptions of the instruction set for the processor on the
PulseBlaster board and the C functions in SpinAPI that utilize them. The information on the
instruction set is very in depth and knowledge of this is essential to be able to properly operate the
board. Details of the instruction set architecture are provided first so that the user can understand the
functionality of the PulseBlaster. The second part provides information about SpinCore's Application
Programming Interface (API) package, called SpinAPI.
Instruction Set Architecture
Machine-Word Definition
The PulseBlaster pulse timing and control processor implements an 80-bit wide Very Long
Instruction Word (VLIW) architecture. The VLIW memory words have specific bits/fields dedicated to
specific purposes, and every word should be viewed as a single instruction of the micro-controller.
The maximum number of instructions that can be loaded to on-chip memory is equal to the memory
size described in the model number (i.e., 4k memory words for Model PB24-100-4k, 32k memory
words for Model PB24-100-32k, etc.). The execution time of instructions can be varied and is under
(self) control by one of the fields of the instruction word – the shortest being five clock cycles for the
“Internal Memory Model” and nine clock cycles for the “External Memory Model.” All instructions have
the same format and bit length, and all bit fields have to be filled. Figure 14 shows the fields and bit
definitions of the 80-bit instruction word.
Breakdown of 80-bit Instruction Word
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Figure 14:
Bit definitions of the 80-bit instruction/memory word.
Bit Definitions for the 80-bit Instruction Word (VLIW)
Output/Control Word
| Data Field
| OP Code
| Delay Count
(24 bits) (20 bits) (4 bits) (32 bits)
