PulseBlaster
NOTE:
The PulseBlaster requires a 3.3V input signal for HW_Trigger.
Applying voltages to the
input pins that are greater than 3.3V or less than 0V
will damage the PulseBlaster
.
Figure 12, below, shows an example of the HW_Trigger signal with a latency of 80 ns. Please
refer to the Instruction Set Architecture section in Appendix I for more details on programming the
duration of the WAIT latency. To trigger once, the trigger signal must begin at high voltage (between
2V and 3.3V), then must be pulled low (to ground) and stay low for at least 10 ns before returning to
high voltage. The PulseBlaster will continue to trigger or reset for as long as the HW_Trigger or
HW_Reset signals stay at ground. If using a long TTL cable, make sure it is terminated and a buffer is
used. If necessary, use an inverter or program the triggering device to match the high-low-high
HW_Trigger signal. The input impedance of the HW_Trigger pin is 10 kOhms.
SP17 and PulseBlaster PCIe models have two hardware reset pins.
HW_Reset
is pulled to high
voltage (3.3V) on the board and can be activated by a low voltage pulse (or shorting to GND, e.g., pin
7).
HW_Reset_H
is pulled to low voltage on the board (ground) and can be activated by a high
voltage pulse (to 3.3V). When the signal is activated during the execution of a program, the controller
resets itself back to the beginning of the program. Program execution can be started from the
beginning by either a software start command (pb_start()) or by a hardware trigger.
NOTE:
The PulseBlaster requires a 3.3V input signal for HW_Reset.
Applying voltages to the
input pins that are greater than 3.3V or less than 0V
will damage the PulseBlaster
.
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Figure 12:
Demonstration of HW_Trigger high-low-high signal. The blue
shows the HW_Trigger signal, the pink shows one of the output flags
Caution: applying voltages to the input pins that are greater than 3.3V
or less than 0V will damage the PulseBlaster.
