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M2i.30xx / M2i.30xx-exp Manual
Limits of pre trigger, post trigger, memory size
Mode Gated Sampling
Limits of pre trigger, post trigger, memory size
The maximum memory size parameter is only limited by the number of activated channels and by the amount of installed memory. Please
keep in mind that each sample needs 2 bytes of memory to be stored. Minimum memory size as well as minimum and maximum post trigger
limits are independent of the activated channels or the installed memory.
Due to the internal organization of the card memory there is a certain stepsize when setting these values that has to be taken into account.
The following table gives you an overview of all limits concerning pre trigger, post trigger, memory size, segment size and loops. The table
shows all values in relation to the installed memory size in samples. If more memory is installed the maximum memory size figures will increase
according to the complete installed memory
Running the card with a sampling rate that is above 100 MS/s switches the cards internally to an interlace mode. In this mode two ADCs
are running in parallel using a 180° shifted signal. Due to the fact that two ADCs are running this mode has a little different limitations and
is listed separately in the following table.
All figures listed here are given in samples. An entry of [8k - 16] means [8 kSamples - 16] = [8192 - 16] = 8176 samples.
The given memory and memory / divider figures depend on the installed on-board memory as listed below:
Please keep in mind that this table shows all values at once. Only the absolute maximum and minimum values are shown. There might be
additional limitations. Which of these values is programmed depends on the used mode. Please read the detailed documentation of the mode.
Gated Sampling and Timestamps
Gated Sampling and the timestamp mode fit very good together. If timestamp
recording is activated each gate will get timestamped as shown in the draw-
ing on the right. As you can see, both beginning and end of the gate interval
are timestamped. Each gate segment will therefore produce two timestamps
showing start of the gate interval and end of the gate interval. By taking both
timestamps into account one can read out the time position of each gate as
well as the length in samples. There is no other way to examine the length of
each gate segment than reading out the timestamps.
Please keep in mind that the gate signals are timestamped, not the beginning
and end of the acquisition. The first sample that is available is at the time po-
sition of [Timestamp1 - Pretrigger]. The last sample of the gate segment is at the position [Time Posttrigger]. The length of the gate
segment is [Timestamp2 - Time Pret Posttrigger]. When using the standard gate mode the end of recording is defined by
the expiring memsize counter. In standard gate mode there will be an additional timestamp for the last gate segment, when the maximum
memsize is reached!
Activated
Used
Memory size
Pre trigger
Post trigger
Segment size
Loops
Channels
Mode
SPC_MEMSIZE
SPC_PRETRIGGER
SPC_POSTTRIGGER
SPC_SEGMENTSIZE
SPC_LOOPS
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
Min
Max
Step
1 channel
Standard Single
8
Mem
4
defined by post trigger
4
8G - 4
4
not used
not used
Standard Multi/ABA 8
Mem
4
4
8k - 16
4
4
Mem/2-4 4
8
Mem/2
4
not used
Standard Gate
8
Mem
4
4
8k - 16
4
4
Mem-4
4
not used
not used
FIFO Single
not used
4
8k - 16
4
not used
8
8G - 4
4
0 (
∞
)
4G - 1
1
FIFO Multi/ABA
not used
4
8k - 16
4
4
8G - 4
4
8
Mem/2
4
0 (
∞
)
4G - 1
1
FIFO Gate
not used
4
8k - 16
4
4
8G - 4
4
not used
0 (
∞
)
4G - 1
1
Interlace
Standard Single
16
Mem
8
defined by post trigger
8
8G - 4
8
not used
not used
Standard Multi/ABA 16
Mem
8
8
8k - 16
8
8
Mem/2-4 8
16
Mem/2
8
not used
Standard Gate
16
Mem
8
8
8k - 16
8
8
Mem-4
8
not used
not used
FIFO Single
not used
8
8k - 16
8
not used
16
8G - 4
8
0 (
∞
)
4G - 1
1
FIFO Multi/ABA
not used
8
8k - 16
8
8
8G - 4
8
16
Mem/2
8
0 (
∞
)
4G - 1
1
FIFO Gate
not used
8
8k - 16
8
8
8G - 4
8
not used
0 (
∞
)
4G - 1
1
2 channels
Standard Single
8
Mem/2
4
defined by post trigger
4
8G - 4
4
not used
not used
Standard Multi/ABA 8
Mem/2
4
4
4k - 8
4
4
Mem/4-4 4
8
Mem/4
4
not used
Standard Gate
8
Mem/2
4
4
4k - 8
4
4
Mem/2-4 4
not used
not used
FIFO Single
not used
4
4k - 8
4
not used
8
8G - 4
4
0 (
∞
)
4G - 1
1
FIFO Multi/ABA
not used
4
4k - 8
4
4
8G - 4
4
8
Mem/4
4
0 (
∞
)
4G - 1
1
FIFO Gate
not used
4
4k - 8
4
4
8G - 4
4
not used
0 (
∞
)
4G - 1
1
4 channels
Standard Single
8
Mem/4
4
defined by post trigger
4
8G - 4
4
not used
not used
Standard Multi/ABA 8
Mem/4
4
4
2k - 4
4
4
Mem/8-4 4
8
Mem/8
4
not used
Standard Gate
8
Mem/4
4
4
2k - 4
4
4
Mem/4-4 4
not used
not used
FIFO Single
not used
4
2k - 4
4
not used
8
8G - 4
4
0 (
∞
)
4G - 1
1
FIFO Multi/ABA
not used
4
2k - 4
4
4
8G - 4
4
8
Mem/8
4
0 (
∞
)
4G - 1
1
FIFO Gate
not used
4
2k - 4
4
4
8G - 4
4
not used
0 (
∞
)
4G - 1
1
Installed Memory
32 MSample
64 MSample
128 MSample
256 MSample
512 MSample
1 GSample
2 GSample
Mem
32 MSample
64 MSample
128 MSample
256 MSample
512 MSample
1 GSample
2 GSample
Mem / 2
16 MSample
32 MSample
64 MSample
128 MSample
256 MSample
512 MSample
1 GSample
Mem / 4
8 MSample
16 MSample
32 MSample
64 MSample
128 MSample
256 MSample
512 MSample
Mem / 8
4 MSample
8 MSample
16 MSample
32 MSample
64 MSample
128 MSample
256 MSample
