Spectrum Digital TMS320DM365, Technical Reference

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Spectrum Digital, Inc
2-6 DM365 EVM Technical Reference
2.1.1.2.1 Register 0, CPLD Version
This read only, 8 bit register, contains the CPLD hardware version for version control.
The default value is 0x11.
2.1.1.2.2 Register 1, Test Register
This read only, 8 bit register, has a default value of 0xA5 and can be read and written to
test the memory interface.
2.1.1.2.3 Register 2, LED Register
This 8 bit, read/write register controls the user LEDs. A data bit of ‘0’ in each bit
location turns on an LED. Similarly a ‘1’ turns off the LED in each bit position.
2.1.1.2.4 Register 3, Board Mux Control Register
This 8 bit, read/write control register (default = 0x00) controls keypad, AIC, SD,
Ethernet, and Video In multiplexers as shown in the table below.
points as shown in the table below.
Table 2: Register 3, Board Mux Control Register
Bit # Signal State Function
7 EMIF_KEYPAD_CTL
0 Addresses on Muxes (ONE NAND Mode)
1 Addresses are available for keypad
6 SEL_SD1_GPIO_CTL
0 Enables SD card slot 1
1 Signals for SD1 card slot 1 go to CPLD
imager GPIO
5 SEL_AICn_GPIO_CTL
0 Enables McBSP signals to AIC3101 codec
1 McBSP signals go to CPLD for imager GPIO
4 Spare Not currently used
3 SEL_ENET_GPIO_CTL
0 Enable Ethernet signals to PHY
1 Ethernet signals go to CPLD for imager GPIO
2 DECODER_IMAGER_S2_CTL
S[2:0]
0 0 1 = Selects TVP7002 as input to DM365
video input port
0 1 0 = Selects imager as input to DM365
video input port
1 0 1 = Selects TVP5146 as input to DM365
video input port
1 DECODER_IMAGER_S1_CTL
0 DECODER_IMAGER_S0_CTL