Theory
91369 Service Manual
3-10
SDRAM Memory
In Normal Operation, the CPU executes code directly from SDRAM.
The 32 MB (256 Mbits) SDRAM is refreshed using its auto-refresh mode. Using the SDRAM’s periodic timer,
an auto refresh command is issued to the SDRAM every 15.6
µ
s.
Static RAM (GDS) Memory
The Static RAM contains Patient Trend Data and Demographics, known as the Global Data System (GDS).
The monitor contains two banks of 256 KB SRAM that hold the GDS data. They draw their power from the 3 V
backup with a minimum of three minutes of battery backup supply, using a SuperCap with the MAXIM 6363
supervisor.
Chip Selects
Chip selects for devices on the 60x bus are generated by the MPC8270 memory controller unit.
The monitor uses only three of the 12 available chip selects:
•
CS0
— Boot Flash (controlled by the GPCM)
•
CS2
— SDRAM (controlled by the SDRAM)
•
CS6
— GDS SRAM (controlled by the GPCM)
MPC8270 Microprocessor
The monitor uses the Motorola MPC8270ZQ processor.
Some of the special features include:
• PowerPC G2_LE core processor unit.
• Separate power supply for the internal logic (1.5 V) and for I/O (3.3 V).
• 64-bit data and 32-bit address on the 60x bus.
• 32-bit address/data on the PCI bus.
• Integrated PCI 2.2 compliant bridge, 32-bit data bus, 66 MHz, 3.3 V.
• Twelve-bank memory controller with glueless interface to SRAM, SG1DRAM, and Flash.
• Embedded 32-bit RISC architecture communication processor.
Ethernet Interface
The MPC8270 contains fast ports on its communication module. The monitor takes advantage of one FCC
standard port (FCC1) for the 10/100BaseT Ethernet port. The interface to the Physical Layer (PHY) is through
full Media Independent Interface (MII). Data communication is in Nibble mode (4 TX_D lines and 4 RX_D
lines). The RJ-45 connector contains LEDs indicating speed (yellow ON for 100 MHz, yellow OFF for 10 MHz)
and link status (green flashing about once every five seconds for Link Active).
