XDP-PK1000
26
Pin No.
Pin Name
I/O
Description
59
DAO4 (R_L-CH)
O
Rear L-channel data output terminal Not used
60
DVDD5
-
Power supply terminal (+3.3V)
61
DAO5 (SUB-CH)
O
Sub channel data output terminal Not used
62
DVSS5
-
Ground terminal
63
VDD1-3
-
Power supply terminal (+1.5V)
64
VSS-2
-
Ground terminal
65
XVSS3
-
Ground terminal
66
XI
I
System clock input terminal (16.934 MHz)
67
XO
O
System clock output terminal (16.934 MHz)
68
XVDD3
-
Power supply terminal (+3.3V)
69
ADVDD3
-
Power supply terminal (+3.3V)
70
ADIN1 (IN_L-CH)
I
Audio signal (L-channel) input terminal Not used
71
ADVREFL
O
Reference voltage (+1.65V) output terminal Not used
72
ADVCM
O
Reference voltage (+1.65V) output terminal Not used
73
ADVREFH
O
Reference voltage (+1.65V) output terminal Not used
74
ADIN2 (IN_R-CH)
I
Audio signal (R-channel) input terminal Not used
75
ADVSS3
-
Ground terminal
76
MS
I
I/F mode selection signal input terminal Fixed at “H” in this unit
77, 78
BUS0, BUS1
I/O
Bus data input/output with the iPod/iPhone controller
79
BUS2/So
I/O
Bus data input/output with the iPod/iPhone controller
80
BUS3/Si
I/O
Bus data input/output with the iPod/iPhone controller
81
BUCK/SCL
I
Bus clock signal input from the iPod/iPhone controller
82
/CCE
I
Chip enable signal input from the iPod/iPhone controller
83
VDD3-2
-
Power supply terminal (+3.3V)
84
VSS-3
-
Ground terminal
85
/RST
I
Reset signal input from the iPod/iPhone controller “L”: reset
86
VDD1-4
-
Power supply terminal (+1.5V)
87
DEC_REQ
O
Request signal output to the iPod/iPhone controller
88
BSIF-REQ
O
Request signal output to the iPod/iPhone controller
89
BSIF-GATE
I
Gate signal input from the iPod/iPhone controller
90
BSIF_DATA
I
Audio data input from the iPod/iPhone controller
91
BSIF_BCK
I
Bit clock signal input from the iPod/iPhone controller
92
BSIF_LRCK
I
L/R sampling clock signal input from the iPod/iPhone controller
93
DEC_XMUTE
I
Muting on/off control signal input from the iPod/iPhone controller “H”: muting on
94
ZDET
O
Zero detection signal output to the iPod/iPhone controller
95
CD-MON0/SP_DATA
O
Spectrum analyzer data output terminal Not used
96
CD-MON1/SP_CLK
I
Spectrum analyzer data transfer clock signal input terminal Not used
97
TEST
I
Test mode setting signal input terminal Normally
fi
xed at “L”
98
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal Not used
99
TMAX
O
TMAX detection result output terminal Not used
100
LPFN
I
Inverted signal input for PLL loop
fi
lter from the operation ampli
fi
er Not used