1-35
IC
VGN-
S36C/S36GP/S36LP/S36SP/S36TP/S38CP/
S52B/
S62PS/S62PSY/S62S/
S350F/S350FP/
S360/S360P/
S370F
(J/AM
/AO
)
Confidential
2.3. Hub
Interface
Signals
Note:
Unless otherwise specified, the voltage level for all signals in this interface is 1.8 Volts.
Table 6. Hub Interface Signal Descriptions
Signal Name
Type
Description
HI_[10:0]
I/O
CMOS
Hub Interface Signals:
Signals used for the hub interface.
HI_STB
I/O
CMOS
Hub Interface Strobe:
One of two differential strobe signals used to transmit or
receive packet data over hub interface.
HI_STB#
I/O
CMOS
Hub Interface Strobe Complement:
One of two differential strobe signals used to
transmit or receive packet data over hub interface.
2.4. AGP
Interface
Signals
Note:
Unless otherwise specified, the voltage level for all signals in this interface is 1.5 Volts (VCC1_5).
2.4.1.
AGP Addressing Signals
Table 7. AGP Addressing Signal Descriptions
Signal Name
Type
Description
PIPE#
I
AGP
Pipelined Read:
This signal is asserted by the AGP master to indicate a full width
address is to be enqueued on by the target using the AD bus. One address is placed
in the AGP request queue on each rising clock edge while PIPE# is asserted. When
PIPE# is deasserted no new requests are queued across the AD bus.
During SBA Operation:
This signal is
not used
if SBA (Side Band Addressing) is
selected.
During FRAME# Operation:
This signal is
not used
during AGP FRAME#
operation.
PIPE#
is a sustained tri-state signal from masters (graphics controller), and is an
input to the MCH.
SBA[7:0]
I
AGP
Side-band Address:
These signals are used by the AGP master (graphics
controller) to pass address and command to the MCH The SBA bus and AD bus
operate independently. That is, transactions can proceed on the SBA bus and the
AD bus simultaneously.
During PIPE# Operation:
These signals are
not used
during PIPE# operation.
During FRAME# Operation:
These signals are
not used
during AGP FRAME#
operation.
NOTE:
When sideband addressing is disabled, these signals are isolated (no
external/internal pull-ups are required).
The above table contains two mechanisms to queue requests by the AGP master. Note that the master
can only use one mechanism. The master may not switch methods without a full reset of the system.
When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus.
For example, during configuration time, if the master indicates that it can use either mechanism, the
configuration software will indicate which mechanism the master will use. Once this choice has been
made, the master will continue to use the mechanism selected until the master is reset (and
reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a
static decision when the device is first being configured after reset.
2.4.2.
AGP Flow Control Signals
Table 8. AGP Flow Control Signals
Signal Name
Type
Description
RBF#
I
AGP
Read Buffer Full:
Read buffer full indicates if the master is ready to accept
previously requested low priority read data. When RBF# is asserted the MCH is not
allowed to initiate the return low priority read data. That is, the MCH can finish
returning the data for the request currently being serviced. RBF# is only sampled at
the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required
to implement this signal.
During FRAME# Operation:
This signal is not used during AGP FRAME#
operation.
WBF#
I
AGP
Write-Buffer Full:
indicates if the master is ready to accept Fast Write data from
the MCH. When WBF# is asserted the MCH is not allowed to drive Fast Write data
to the AGP master. WBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data then it is not required to
implement this signal.
During FRAME# Operation:
This signal is not used during AGP FRAME#
operation.
2.4.3.
AGP Status Signals
Table 9. AGP Status Signal Descriptions
Signal Name
Type
Description
ST[2:0 Meaning
000
Previously requested low priority read data is
being returned to the master
001
Previously requested high priority read data is
being returned to the master
010
The master is to provide low priority write data
for a previously queued write command
011
The master is to provide high priority write data
for a previously queued write command.
100 Reserved
101 Reserved
110 Reserved
ST[2:0]
O
AGP
Status:
Provides
information from the
arbiter to an AGP
Master on what it
may do. ST[2:0]
only have meaning
to the master when
its GNT# is
asserted. When
GNT# is deasserted
these signals have
no meaning and
must be ignored.
110
The master has been given permission to start a
bus transaction. The master may queue AGP
requests by asserting PIPE# or start a PCI
transaction by asserting FRAME#
.
2.4.4. AGP
Strobes
Table 10. AGP Strobe Descriptions
Signal Name
Type
Description
AD_STB0
I/O
(s/t/s)
AGP
Address/Data Bus Strobe-0:
provides timing for 2x and 4x data on AD[15:0] and
C/BE[1:0]# signals. The agent that is providing the data will drive this signal.
AD_STB0#
I/O
(s/t/s)
AGP
Address/Data Bus Strobe-0 Complement:
With AD STB0, forms a differential
strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals.
The agent that is providing the data will drive this signal.
AD_STB1
I/O
(s/t/s)
AGP
Address/Data Bus Strobe-1:
Provides timing for 2x and 4x data on AD[31:16] and
C/BE[3:2]# signals. The agent that is providing the data will drive this signal.
AD_STB1#
I/O
(s/t/s)
AGP
Address/Data Bus Strobe-1 Complement:
With AD STB1, forms a differential
strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals
in 4X mode. The agent that is providing the data will drive this signal.
SB_STB
I
AGP
Sideband Strobe:
Provides timing for 2x and 4x data on the SBA[7:0] bus. It is
driven by the AGP master after the system has been configured for 2x or 4x
sideband address mode.
SB_STB#
I
AGP
Sideband Strobe Complement:
The differential complement to the SB_STB
signal. It is used to provide timing 4x mode.
2.4.5. AGP/PCI
Signals-Semantics
For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate
similarly to their semantics in the PCI 2.1 specification, as defined below.
Table 11. AGP/PCI Signals-Semantics Descriptions
Signal Name
Type
Description
G_FRAME#
I/O
s/t/s
AGP
G_FRAME:
Frame.
During PIPE# and SBA Operation:
Not used by AGP SBA and PIPE# operations.
During Fast Write Operation:
Used to frame transactions as an output during Fast
Writes.
During FRAME# Operation:
G_FRAME# is an output when the MCH acts as an
initiator on the AGP Interface. G_FRAME# is asserted by the MCH to indicate the
beginning and duration of an access. G_FRAME# is an input when the MCH acts
as a FRAME#-based AGP target. As a FRAME#-based AGP target, the MCH
latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which
MCH samples FRAME# active.
G_IRDY#
I/O
s/t/s
AGP
G_IRDY#:
Initiator Ready.
During PIPE# and SBA Operation:
Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation:
G_IRDY# is an output when MCH acts as a
FRAME#-based AGP initiator and an input when the MCH acts as a FRAME#-
based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based
AGP bus initiator's ability to complete the current data phase of the transaction.
During Fast Write Operation:
In Fast Write mode, G_IRDY# indicates that the
AGP-compliant master is ready to provide all write data for the current transaction.
Once G_IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The master is never allowed to insert a wait state during the initial data
transfer (32 bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.
G_TRDY#
I/O
s/t/s
AGP
G_TRDY#:
Target Ready.
During PIPE# and SBA Operation:
Not used while enqueueing requests via AGP
SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions.
During FRAME# Operation:
G_TRDY# is an input when the MCH acts as an AGP
initiator and is an output when the MCH acts as a FRAME#-based AGP target. The
assertion of G_TRDY# indicates the target’s ability to complete the current data
phase of the transaction.
During Fast Write Operation:
In Fast Write mode, G_TRDY# indicates the AGP-
compliant target is ready to receive write data for the entire transaction (when the
transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes.
The target is allowed to insert wait states after each block (32 bytes) is transferred
on write transactions.
G_STOP#
I/O
s/t/s
AGP
G_STOP#:
Stop.
During PIPE# and SBA Operation:
This signal is not used during PIPE# or SBA
operation.
During FRAME# Operation:
G_STOP# is an input when the MCH acts as a
FRAME#-based AGP initiator and is an output when the MCH acts as a FRAME#-
based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on
the AGP interface.
