1-10
IC
VGN-
S36C/S36GP/S36LP/S36SP/S36TP/S38CP/
S52B/
S62PS/S62PSY/S62S/
S350F/S350FP/
S360/S360P/
S370F
(J/AM
/AO
)
Confidential
DESCRIPTION
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
2
3
4
5
6
7
8
9
10
11
12
13
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
/CAS
/RAS
/CS
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
/W/E
NC
NC
VDDQ
DM0
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
NC
VSSQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
VDDQ
DQ3
VSSQ
VSSQ
VSS
Thermal
A10
A2
A1
DQ1
DQ2
VDD
VSS
VDD
A11
A3
VDDQ
DQ0
VDD
VSS
VDD
A9
A4
VDDQ
DQ31
VSSQ
VSSQ
NC
2
A5
A6
DQ30
DQ29
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
3
A7
VDDQ
DQ28
VSSQ
VDD
VDD
CLK
A8/AP
NC
VSSQ
DQ26
VDDQ
NC
/CLK
CKE
VDDQ
DM3
DQ25
DQ24
NC
MCL,
DSF
VREF
DQ27
DQS3
VDDQ
VDDQ
NC
VDDQ
VDDQ
DQ14
DQ12
DQS1
DQ10
DQ8
DQ15
DQ13
DM1
DQ11
DQ9
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
VSS
14
1
P
A
Note :
1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.
2. Ball L9(NC2) is reserved for A12.
3. Ball M10(NC3) is reserved for BA2.
HY5DU283222AFP-33 (HYNIX)
128M (4Mx32) DDR SDRAM
– TOP VIEW –
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM0 ~ DM3
Input
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
DQS0 ~ DQS3
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
DQ0 ~ DQ31
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
FUNCTIONAL BLOCK DIAGRAM
4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM
Command
Decoder
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM(0~3)
Address
Buffer
A0-11
Bank
Control
1Mx32/Bank0
Column Decoder
Column Address
Counter
Sense
AMP
2-bi
t Prefetc
h
Uni
t
1Mx32 /Bank1
1Mx32 /Bank2
1Mx32 /Bank3
Mode
Register
Row
Decoder
In
p
u
t Bu
ffer
O
u
tp
ut
B
u
ff
er
Data Strobe
Transmitter
Data Strobe
Receiver
DQS(0~3)
DS
Write Data Register
2-bit Prefetch Unit
DS
DQ[0:31]
64
32
32
64
BA0,BA1
DLL
Block
CLK_DLL
CLK,
/CLK
Mode
Register
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A8/
AP
BA
Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
Device Deselect
H
X
H
X
X
X
X
1
No Operation
L
H
H
H
Bank Active
H
X
L
L
H
H
RA
V
1
Read
H
X
L
H
L
H
CA
L
V
1
Read with Autoprecharge
H
1,3
Write
H
X
L
H
L
L
CA
L
V
1
Write with Autoprecharge
H
1,4
Precharge All Banks
H
X
L
L
H
L
X
H
X
1,5
Precharge selected Bank
L
V
1
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Self Refresh
Entry
H
L
L
L
L
H
X
1
Exit
L
H
H
X
X
X
1
L
H
H
H
Precharge Power
Down Mode
Entry
H
L
H
X
X
X
X
1
L
H
H
H
1
Exit
L
H
H
X
X
X
1
L
H
H
H
1
Active Power
Down Mode
Entry
H
L
H
X
X
X
X
1
L
V
V
V
1
Exit
L
H
X
1
Note :
1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
WRITE MASK TRUTH TABLE
Function
CKEn-1
CKEn
/CS, /RAS,
/CAS, /WE
DM(0~3)
ADDR
A8/
AP
BA
Note
Data Write
H
X
X
L
X
1,2
Data-In Mask
H
X
X
H
X
1,2
Note :
1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data.
2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23;
DM3 corresponds to the data on DQ24-Q31.
