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Sony SS-HQ1, Application Notes

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- SS-HQ1 Application Notes - 

Ver.1.0.0 January 7, 2005 

 

24 

 

3.6.3.  If Noise Occurs 

If noise on the screen from in the designed board is confirmed, identify the source of the noise before taking 
appropriate measures. Means of identifying noise sources are described below.   
One method that simplifies checking how noise is generated is to block the lens and set AGC to maximum that 
is, set AGCMAX (CAT14_Byte1_bit4) to 1. This makes investigating noise easier. 

 

1.  Using the pattern generator function 

The pattern generator (PG) function inserts a generated signal immediately after the CXD3172AR's 
internal A/D signal input area. This pattern generator can be used to identify the general area where the 
noise is occurring.   
If the noise is eliminated when the pattern generator is displayed, then the noise is occurring on the 
portion from the CCD to the CXA2096N or on the front end of the CXD3172AR. If the noise remains, it 
may be occurring at a later point (including the CXD3172AR). 
 

2. Separating ECK 

ECK (pin 88) is an input pin for the encoder clock. Depending on the layout of the X'tal oscillator 
connected to this pin, the oscillator clock may become mixed in signal lines and generate noise on the 
screen.  
If so, remove the X'tal and connect the input side (ESCI, pin 86) of the DSP's internal inverter to the 
ground. In this state send the clock from an external source to ECK. If the noise is eliminated, the cause 
of noise is the X'tal oscillator layout or the pattern design of another signal line. 
 

3. Separating VIN 

VIN (pin 3) is an input pin for ADC analog signals. Separate this pin from the CXA2096N and connect it 
to a stabilization DC power supply to check for noise on the screen. If the noise is eliminated, it may be 
occurring at a source closer to the front end than the CXA2096N (including the CCD) before it enters 
the CXD3172AR. If the noise remains the cause may be back-end sites, including the CXD3172AR. 
 

4.  Eliminating the PLL loop 

The PLL circuit, which inputs the clock in MCK (pin 43), performs feedback control to maintain a 
constant phase in the oscillating circuit. If noise enters the PLL circuit control signal, the noise appears 
on screen. In MCK, the PLL oscillator circuit input pin, supply a signal of a fixed wavelength (such as 
the X'tal's) that does not use PLL. Check if the noise is eliminated. If it is, the cause of noise is the 
layout or pattern design of circuits around PLL. 
 

5.  Separating the power supplies 

It is difficult to identify sources of noise propagating over power lines. Therefore, disconnect the primary 
circuit and IC power supplies. Supply power from a clean external source to identify the point where the 
noise is eliminated. 

Summary of Contents for SS-HQ1

Page 1: ... SS HQ1 Application Notes Ver 1 0 0 January 7 2005 i SS HQ1 Application Notes Sony Corporation Semiconductor Solutions Network Company ...

Page 2: ...nal EVR is not used 9 3 2 4 Processing of the power supply Pins for analog cells 9 3 3 Oscillator Circuit Periphery 10 3 3 1 Clock oscillator circuit for 1 clock digital encoder system 10 3 3 2 Clock oscillator circuit for 2 clock ECK master MCK PLL 11 3 4 Reset Circuit 14 3 4 1 Outline 14 3 4 2 Example Circuit and Timing Chart 14 3 4 3 ICs Requiring Reset after Power On 15 3 5 EVR Connection 16 3...

Page 3: ...D Type Selection 39 6 1 Supported CCD type 39 6 2 List of Clock Configurations for Each CCD type 40 6 3 Important information on Wiring 41 6 3 1 Drive Circuit Changes 41 6 3 2 Clock System Changes 44 6 3 3 Frequency Response Changes 44 6 3 4 Clock System Selection 45 6 3 5 Wiring Changes When EEPROM is not written 46 6 4 CCD Primary Color Separation Matrix 47 6 4 1 The Sequence of Parameter Change...

Page 4: ...river Setting Example 81 10 1 8 Conditions for Disabling the Port Drivers 82 10 2 Y Signal Processing 83 10 2 1 Y Luminance Signal Processing Flow 83 10 2 2 Pre Block Signal Processing 83 10 2 3 Y Signal Main Process 86 10 2 4 High resolution mode 89 10 2 5 Aperture Compensation Function 91 10 3 Chroma Signal Processing 93 10 3 1 Block diagram 93 10 3 2 Complementary Color Pixel Clipping 94 10 3 3...

Page 5: ...ish detection and compensation 156 11 2 1 CCD blemish detection method types 156 11 2 2 Blemish detection and compensation parameters 157 11 2 3 Static detection and compensation function 158 11 2 4 Dynamic detection and compensation function 165 11 2 5 False blemish generating function 173 11 3 Adjustment of TG Phase 174 11 3 1 Adjustment method of phase and drive ability 174 12 Supporting Functi...

Page 6: ... 227 12 3 3 External Synchronization Phase Adjustment through Key Operations 229 12 3 4 WB Gain Adjustment through Key Operations 230 12 4 When Using the External Microcomputer 231 12 4 1 External Microcomputer SS HQ1 System Interface 231 12 4 2 Communication Protocol with External Microcomputers 232 12 5 Pattern Generator PG 239 12 5 1 Pattern generator PG Usage Method 239 12 5 2 Pattern settings...

Page 7: ...d Package LQFP 100pin LQFP 100pin Horizontal resolution Excellent Good Blemish detection and compensation Static Dynamic detection maximum 32 points Compensation only maximum 2 points no detection Privacy masking Up to 8 locations can be set None Mirror Function None Port Driver 16 ports None External synchronization LL VS VBS VRHR LL VS VBS VRHR Pre White Balance Adjustment Semi auto Manual Color...

Page 8: ...lor rolling suppression Allows a color rolling only operation frame to be set in addition high precision high speed operation control MODESEL control Automatic control of system related parameters Automatically changes parameters which have different settings depending on the particular clock system Internal burst separator Extracts burst signal for VBS Lock Extracts a burst signal from an incomin...

Page 9: ...hat supports RS 232C and microcomputer communication 14 Built in ITU REC656 conformity digital output function 15 Built in ITU REC601 conformity digital output function LQFP 100 pin CDS AGC CXA2096N 1 Correlated double sampling CDS 2 Built in AGC circuit 3 Built in interface circuit for A D converter SSOP 24 pin Please refer to the specification of each LSI about detail The peripheral ICs shown in...

Page 10: ...camera DSP CXD3172AR External EVRs shown in Table 2 1 3 are possible to use as peripheral IC Table 2 1 3 Peripheral IC External EVR Peripheral IC Type name Brand name Description Package External EVR MB88347LPFV Fujitsu Device Inc 8bit D A Converter built in 8sets Power supply 3 3V SSOP 16pin ...

Page 11: ...ted by using both the clock ECK which is for encoder oscillated by the crystal and the clock MCK which is for driving system oscillated by the PLL Fig 2 2 2 Signal path of 2 clock ECK master MCK PLL system CCD CDS AGC CXA2096N CXD3172AR EEPROM Y analog output Signal Control signal C analog output Switches TG V Driver EVR A D D A D A DSP PC External Microcomputer RS 232C X tal ECK RS 232C Level Shi...

Page 12: ...One is the output which is compliant with ITU REC656 The other is the output which is compliant with ITU REC601 Fig 2 3 2 Signal Path of Digital Output System CCD CDS AGC CXA2096N CXD3172AR EEPROM YCMIX analog output Signal Control signal Switches TG V Driver EVR A D D A D A DSP PC External Microcomputer RS 232C X tal ECK RS 232C Level Shift CCD CDS AGC CXA2096N CXD3172AR EEPROM Signal Control sig...

Page 13: ...lly Occupied Terminals Pin Name Pin No Parameter Name Description P0 91 P1 92 P2 93 AWBMODE AWB operation mode switching P3 94 CRLESSON Switches anti color rolling mode ON and OFF P4 96 BLCOFF Switches backlight compensation ON and OFF P5 97 AEREF Switches AE reference ON and OFF P6 98 NORMFLC Switches the flickerless function ON and OFF P7 99 AGCMAX Switches the AGC maximum value ON and OFF P8 76...

Page 14: ... VBS Lock VRHR Digital output TEST1 12 GND GND GND GND GND GND GND PCOMP 42 OPEN MCK 43 GND S0 44 3 3V 3 3V 3 3V S1 46 OPEN OPEN OPEN OPEN S2 47 OPEN OPEN OPEN OPEN OPEN S3 48 OPEN OPEN OPEN OPEN OPEN OPEN PCK 51 OPEN OPEN OPEN OPEN OPEN OPEN OPEN VCTRLIN 53 GND GND GND GND GND GND GND CPOUT 54 GND GND GND GND GND GND GND EXVIDEOY 57 3 3V 3 3V 3 3V 3 3V 3 3V EXVIDEO 58 3 3V 3 3V 3 3V 3 3V 3 3V 3 3...

Page 15: ... VGY 72 3 3V VREFY 73 IREFY 71 GND 3 2 3 Processing of Empty Pins in case Internal EVR is not used When Internal EVR are not used Perform pin processing for the CXD3172AR as follows Table 3 2 4 Processing of Empty Pins in case Internal EVR is not used Pin Name Pin No When Internal EVR is not used EVR0 63 EVR1 64 EVR2 66 Connects with GND through 0 1uF capacitor 3 2 4 Processing of the power supply...

Page 16: ...ernal generation in the CXD3172AR of the clock that drives the system Fig 3 3 1 shows the composition of an oscillator circuit using X tal Fig 3 3 1 X tal Oscillator Circuit Configuration Evaluation Board Table 3 3 1 X tal Oscillating Frequency Number of pixels TV System X1 NTSC 38 13986MHz 510H PAL 37 87500MHz NTSC 28 63636MHz 760H PAL 28 37500MHz CXD3172AR 87 ESCO 86 ESCI 1M X1 20p 1000p ECK 88 ...

Page 17: ...ion board circuit constants Table 3 3 2 for a clock oscillator circuit for MCK PLL using X tal Fig 3 3 2 Configuration of Clock Oscillator Circuit for 2 Clock ECK Master MCK PLL Using X tal Oscillation Table 3 3 2 Evaluation Board Circuit Constants R1 TV System X1 VH 15V VH 12V C1 NTSC 0 01uF PAL See Table 3 3 1 56k 47k 1uF CXD3172AR 42 43 PCOMP MCK 10k 10k C1 1M 10k 2SC2412 10k 1u R1 VH 100k 1000...

Page 18: ...ng LC Fig 3 3 3 Configuration of Clock Oscillator Circuit for 2 Clock ECK Master MCK PLL Using LC Oscillation Table 3 3 3 Evaluation Board Circuit Constants R1 TV System VH 15V VH 12V NTSC PAL 56k 47k CXD3172AR 42 43 PCOMP MCK 10k 10k 3 3u 1M 10k 2SC2412 10k 1u R1 VH 100k 1000p 1M 3 3u 20p 10p 1000p 3 3u 100 12p 87 ESCO 86 ESCI 1M X1 20p 1000p ECK 88 20p 150 TC7SU69F TC7SA04F MA2Z365 ...

Page 19: ...ance guarantee is implied for different board layouts component selection or temperature characteristics For VCO circuits LC and X tal oscillation circuits are available Choose the one that suits your application Table 3 3 4 Components Used on the Evaluation Board Component name Manufacturer Model Frequency Load capacitance 28 63636MHz 28 37500MHz 38 13986MHz Crystal oscillator RIVER ELETEC CORPOR...

Page 20: ...reset circuit is shown in Fig 3 4 1 Example Reset Circuit and the timing chart is shown in Fig 3 4 2 If the 3 3V voltage supply surges to exceed 2 7V after power is supplied or other events set the CXD3172AR XRST terminal to Low at least 500ns and be sure to reset it Additionally if the 3 3V power supply falls under 2 7V set the XRST terminal to Low and be sure to reset it The guaranteed voltage f...

Page 21: ...r 1 0 0 January 7 2005 15 Fig 3 4 2 Timing Chart 3 4 3 ICs Requiring Reset after Power On Of the ICs used by the SS HQ1 system only CXD3172AR must be reset 1 2 3 500nsec or more TIME sec Vcc Vout VOLTAGE V 3 3 500nsec or more 2 7 ...

Page 22: ...7 Control parameter value of EVR1 User adjusted EVR2 66 EVR2CNT CAT8_Byte5_bit0 7 Control parameter value of EVR2 User adjusted We recommend connecting EVR0 Pin 63 to AGCCONT Pin 14 of the CXA2096N unless an external microcomputer or other means is used for AGC because AGC of the CXA2096N is performed by the CXD3172AR firmware EVR0 output can be controlled on a per field basis EVR1 and EVR2 Pins 6...

Page 23: ...setting If no control is needed any suitable setting values can be designated in each channel parameter or the channels can be set to standby If channels are set for standby as shown in Table 3 5 3 Integrated EVR Standby Settings the each channel state will be undefined However even when not using integrated EVR a power supply is supplied to the power supply terminal AVD6 74pin AVD6 serves as a D ...

Page 24: ... EVRUSR2 CAT18_Byte10_bit0 7 AO4 4 EVRUSR3 CAT18_Byte11_bit0 7 Output from each field AO5 5 EVRUSR4 CAT18_Byte12_bit0 7 AO6 6 EVRUSR5 CAT18_Byte13_bit0 7 AO7 7 EVRUSR6 CAT18_Byte14_bit0 7 AO8 10 EVRUSR7 CAT18_Byte15_bit0 7 User adjustable value 0h FFh Output from groups of four fields External EVR Communication Control Each field is used in communication between the CXD3172AR and an external EVR M...

Page 25: ..._bit1 Chip Selection signal output pin Parameter setting Setting value 0 h S4 49pin S4SEL CAT1_Byte8_bit6 7 0 h 1 h P3 94pin Multiple signals can be sent from pin S4 so additional parameter settings besides CSEVRSEL are required To send the chip selection signal use the settings shown in the above table For output from pin P3 making CSEVRSEL 1 h will send the chip selection signal Thus other param...

Page 26: ...wiring because the CXD3172AR includes several analog cells for A D D A EVR and other functions In particular do not arrange the oscillator for the encode clock connected to ESCI ESCO and ECK pins 86 87 and 88 respectively or the pattern route near the pins or pattern used for the analog cell This may cause noise so position the oscillator as close as possible to the ESCI ESCO and ECK pins For syst...

Page 27: ...096N and Surrounding Areas 1 For the power supply of VCC pins 5 16 and 23 connect LC filters to prevent crosstalk from other circuits causing interference Additionally connect bypass capacitors between each pin and ground 2 PIN and DIN pins 21 and 22 are input pins for the CCD signal so make the signal lines from the CCD as short as possible and surround them with a ground shield 3 VRB and VRT pin...

Page 28: ...form duty delay and drivability to match the waveform conditions of the clock driving the CCD If connectors are used in the connection with the CCD element use a ground shield between signals to prevent signal degradation For the connectors provide many ground pins to strengthen the earth coupling Furthermore shorten the H1 and H2 wiring length between ICs as much as possible Before use make sure ...

Page 29: ...1 uF between each pin and ground 10 ECK pin 88 is an input pin for the encoder clock that is for X tal oscillator input Make the signal line as short as possible and surround it with a ground shield so that it will not be affected by nearby circuits We also recommend positioning X tal components and the board s inner layer away from other circuits and removing the board s inner layer pattern so th...

Page 30: ...onnect the input side ESCI pin 86 of the DSP s internal inverter to the ground In this state send the clock from an external source to ECK If the noise is eliminated the cause of noise is the X tal oscillator layout or the pattern design of another signal line 3 Separating VIN VIN pin 3 is an input pin for ADC analog signals Separate this pin from the CXA2096N and connect it to a stabilization DC ...

Page 31: ...necting an external LPF makes it impossible to obtain high resolution due to attenuation of the luminance signal 3 8 Example Characteristics and Circuit for External BPF 3 8 1 Outline In cases where the CXD3172AR s chroma signal output pin IOC Pin 67 is used add a band pass filter circuit to ensure that signal components other than the sub carrier component are removed This circuit also shapes the...

Page 32: ...red on an evaluation board using the BPF formed in Fig 3 8 1 Fig 3 8 2 Example BPF Frequency Characteristics NTSC Fig 3 8 3 Example BPF Frequency Characteristics PAL NTSC BPF 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY MHz GAIN dB 3 58MHz PAL BPF 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY MHz GAIN dB 4 43MHz ...

Page 33: ...thod for output from the CXD3172AR Refer to Table 3 9 1 below to set the appropriate setting for the output method you want to use It is not necessary to connect an external LPF in either case Table 3 9 1 DAC Mode Selection Method Description Parameter Setting value DAC1 DAC2 0 h Composite output Not used DACMODE CAT1_Byte3_bit2 1 h Component Y output Component C output DAC1 IOY VREFY VGY IREFY DA...

Page 34: ...put and adjust the voltage as appropriate Note that the voltage input to the VREFY VREFC pins must be in the range of 0 6 to 1 1V based on the specifications for the CXD3172AR s internal DAC Therefore use a configuration in which an amplifier circuit is placed in the final stage Note that proper operations cannot be guaranteed if the voltage is input using any other type of configuration Fig 3 9 1...

Page 35: ...d The signal level output from the IOY pin changes depending on the setting for the voltage being input to the VREFY pin Input and adjust the voltage as appropriate Note that the voltage input to the VREFY pin must be in the range of 0 6 to 1 1V based on the specifications for the CXD3172AR s internal DAC Therefore use a configuration in which an amplifier circuit is placed in the final stage Note...

Page 36: ...LPF is required even when using high resolution Table 3 10 1 summarizes the optical LPFs used with our evaluation board for your reference Table 3 10 1 CCD Types and Optical LPF Model Numbers CCD Type Optical size Optical LPF Model Number 1 3 SV T634A 510H 1 4 SV T635A 1 3 SV T636AS 760Ｈ 1 4 SV T618S made by KYOCERA KINSEKI Corporation Sony uses the optical LPFs three layer configuration shown in ...

Page 37: ... CAT14 AE2 Parameters related to AE 2 CAT15 AWB2 Parameters related to AWB 2 CAT16 OPDWIND2 Parameters related to OPD window 2 CAT17 EXTSYNC2 Parameters related to external synchronization 2 CAT18 FEADJ EVREXT Parameters related to external EVR CAT19 PREADJ Parameters related to line adjustment CAT20 PORT Port driver setting parameters CAT21 BLMDET2 Parameters related to blemish detection and comp...

Page 38: ...al The values reflected by firmware application may be overwritten again Take care to ensure that controls are not duplicated while setting the port drivers Execute commands through communication from PC or external microcomputer It is recommended that the execution of firmware application or execution of port drivers be stopped in order to correctly reflect the parameter overwrite command These s...

Page 39: ... Description of Operation of Each Function 11 Functions for Adjustment and 12 Supporting Functions for applications 4 3 Parameter Changes through Communication Parameter changes are made by executing commands through communication from PC or external microcomputer For details of communication commands refer to 9 1 4 Communication Format of 9 1 RS 232C Communication and 12 4 2 Communication Protoco...

Page 40: ...ping is performed in 1 byte units therefore the address length becomes 512 words x 2 bytes 1024 bytes address 0 3FF h Table 4 4 1 EEPROM Map of SS HQ1 System Map Address contents EEP Word 000h 001h Chip_ID code 000h 002h 131h CAT_12 21 parameters 001h 098h 132h 27Bh CAT_1 4 6 11 24 parameters 099h 13Dh 27Ch 3FFh Prohibition of use 13Eh 1FFh CAT5 undisclosed for firmware control and CAT22 CAT23 ser...

Page 41: ...mary write Execute the EEPROM ALL WRITE command with CPUHOLD 1 h In the SS HQ1 control software click in the following sequence EEPROM sub menu procedure Send Write Read All Select button Start button Immediately after the EEPROM write verify will be executed Confirm that the result shows that all parameters are OK If write is not possible or if an error occurs check whether an EEPROM or serial co...

Page 42: ...itial operations for the DSP CXD3172AR are required after startup Initial operations for the DSP assume that power has been supplied to the CCD and peripheral ICs Connect reset input XRST pin 11 to the reset circuit We recommend that setting parameters of the SS HQ1 system be stored in EEPROM The initialization sequence varies depending on whether or not there are valid parameters in EEPROM Please...

Page 43: ...n routine processing If there is communication with an external microcomputer it starts after the 11th field internal register initialization PDR initialization EVR communication initialization System settings initialization for external communication PDR control Loading of parameters from EEPROM or internal ROM values Assignment of parameters and functions to the port driver CAS I O and CSROM ini...

Page 44: ...EPROM values XRST L reset again read from EEPROM reinitialize Table 5 1 1 Parameters Valid Only during Power on Sequence Initialization Operations CAT Byte Bit Parameter Initial settings 1 0 3 MODESEL Loaded from P12 P15 CAT20 setting 10 0 BPSSEL 1 RS 232C 19200bps 10 1 EVRLDSEL 0 CSROM S4 out 13 1 SYSSELON 0 OFF 13 2 SYSSELFLG 16 0 7 MODESEL0 17 0 7 MODESEL1 18 0 7 SGMODE0 19 0 7 SGMODE1 20 0 7 E...

Page 45: ...were prepared Some types may be added or eliminated due to CCD version upgrades or discontinued production Table 6 1 1 CCD Image Sensors Supported by the SS HQ1 Number of pixels Optical size TV system Product name ICX254AK NTSC ICX404AK ICX255AK Type 1 3 PAL ICX405AK ICX206AK NTSC ICX226AK ICX207AK 510H Type 1 4 PAL ICX227AK ICX258AK NTSC ICX408AK ICX259AK Type 1 3 PAL ICX409AK ICX228AK NTSC ICX27...

Page 46: ...ows 4MCK or 2MCK CXD3172AR 88pin ECK input or CXD3172AR 43pin MCK PLL input 8fsc CXD3172AR 88pin ECK input 27MHz CXD3172AR 88pin ECK input or CXD3172AR 43pin MCK PLL input Table 6 2 1 Relationship between CCD type and Clock Frequencies ECK TV system CCD type MODE SEL 1 8fsc 4MCK 2MCK 27MHz 1MCK PLL input 0 h 38 13986MHz 1 h 28 63636MHz 510H 2 h 27 00000MHz 38 13986MHz 6 h 28 63636MHz NTSC 760H 8 h...

Page 47: ...D type Optical size Product name Vsub voltage RG voltage H RG V Drive circuit example ICX254AK ICX255AK Generated internally adjustment free 5 0V 5 0V 7 0V Fig 6 3 4 ICX404AK Type 1 3 ICX405AK Clamped high adjustment free 5 0V 5 0V 7 0V Fig 6 3 1 ICX206AK ICX207AK 3 3V 3 3V 7 0V Fig 6 3 2 ICX226AK 510H Type 1 4 ICX227AK 3 3V 3 3V 5 0V Fig 6 3 3 ICX258AK ICX259AK Generated internally adjustment fre...

Page 48: ...ig 6 3 2 SS HQ1 CCD Drive Circuit Example ICX206 207AK ICX278 279AK ICX404 405AK ICX408 409AK H2 H1 SUB RG CXD3172AR SUB 36 RG 19 H1 22 H2 23 VH 34 VL 37 AVD2 21 AVS2 24 15V 5V 15V 7 0V 11 15 16 13 ICX206 207AK ICX278 279AK H2 H1 SUB RG CXD3172AR SUB 36 RG 19 H1 22 H2 23 VH 34 VL 37 AVD2 21 AVS2 24 3 3V 15V 7 0V 10 13 14 12 ...

Page 49: ... Fig 6 3 4 SS HQ1 CCD Drive Circuit Example ICX254 255AK ICX258 259AK ICX226 227AK ICX228 229AK H2 H1 SUB RG CXD3172AR SUB 36 RG 19 H1 22 H2 23 VH 34 VL 37 AVD2 21 AVS2 24 3 3V 12V 5 0V 10 13 14 12 ICX254 255AK ICX258 259AK H2 H1 SUB RG CXD3172AR SUB 36 RG 19 H1 22 H2 23 VH 34 VL 37 AVD2 21 AVS2 24 5V 15V 7 0V 11 15 16 13 ...

Page 50: ...e CXD3172AR SUB pin 36 output is input via a capacitor to the CCD s SUB pin The CXD3172AR RG 19pin is input to the CCD after its DC component is cut by a capacitor Fig 6 3 4 SS HQ1 CCD Drive Circuit Example ICX254 255AK ICX258 259AK shows the drive circuit when using 1 3 type CCD image sensors ICX254 255AK ICX258 259AK Both Vsub voltage and RG voltage are adjustment free Vsub is a voltage generate...

Page 51: ...e parameter MODESEL which switches operation modes as the initial setting and pins for the port driver The parameter MODESEL controls CCD types TV system and clock setting in a lump It isn t necessary of resetting these parameters Table 6 3 2 Setting Method of Operation Mode pins P12 15 Clock pin MODESEL P15 84pin P14 83pin P13 82pin P12 80pin TV system CCD ECK 88pin MCK 43pin 0 h Low Low Low Low ...

Page 52: ...h Analog Digital output A h 8fsc Analog output B h 27M master MCK PLL PLL configuration MCK input 6 3 5 Wiring Changes When EEPROM is not written When the effective data are not written to EEPROM set according to the system which uses P12 15 CXD3172AR 80 82 83 and 84pin Wire the VDD side or GND side and set by pull up or pull down so that setting method is shown in the Table 6 3 2 DSP reads the se...

Page 53: ...nded Parameter s Value The spectral characteristics of the color filter differ according to the type of CCD The SS HQ1 initial settings are designed in consideration of the spectral characteristics of a 1 4 type CCD image sensor Therefore resetting the parameters on the following table and writing this data to the EEPROM is recommended when using other types of CCD image sensors Table 6 4 1 CCD Ty...

Page 54: ... FF h The above linear matrix parameters are example setting determined with an emphasis on color reproducibility for skin color in representative samples of each CCD type Please note that they are not intended to be adjusted to the target displayed on the vector scope Use the above linear matrix parameters as reference values In actual practice we recommend that each user set their own values to ...

Page 55: ...Power supply for CXD3172AR V driver shutter driver Power supply for CCD image sensor Power supply for reset gate pulse clamp VL Power supply for CXD3172AR V driver shutter driver Protective transistor input voltage for CCD image sensor Care should be taken as the voltage 5 0V VH VL differs according to the drive specification of the CCD image sensor 7 1 1 Supply Voltage Accuracy When using SS HQ1 ...

Page 56: ...iving ICX408AK Item IC type name Supply voltage Current consumption CCD ICX408AK 15 0V 4 20mA 15 0V 0 18mA 5 0V 33 7mA 3 3V 171 9mA DSP CXD3172AR 7 0V 1 19mA CDS CXA2096N 3 3V 39 3mA The current consumption value of each IC is adding together the analog power supply and the digital power supply 7 1 3 Power on Sequence When turning on the power be sure to turn on the VL last The 3 3V 5 0V and VH po...

Page 57: ...ystem sets up the dynamic range of 2 5 times the standard level A level diagram for an SS HQ1 system is described below The recommended values and signal levels presented here have been verified on our evaluation boards Please note that this is no guarantee of performance including board layout changes parts selection and temperature characteristics 8 1 1 1 The Output of CCD Fig 8 1 2 an example o...

Page 58: ...ject the black level change by noises an offset level can be added to DRVOUT In the black clamping processing of CXD3172AR the offset level is subtracted in the integral mean So the proper signal level is extracted The built in EVR of CXD3172AR can control AGC of CXA2096N by AGCCONT input CCD output level is small and gained up in AGC processing at low light condition If the lowest AGC value is sh...

Page 59: ... signal processing are done in the CXD3172AR Finally processed signals are loaded to built in 10bit DAC and converted to the analog Video signal The digital output signal of built in A D converter contains both of luminance element and chrominance element And the signal is processed suppress aperture compensation and gamma so that the output signal form of DAC may different from the input signal f...

Page 60: ... Analog Circuit of 3 Peripheral Circuits for internal Y DAC peripheral circuit examples and usage notes The chrominance signal is not discussed here because it differs according to the spectral characteristics of the CCD image sensor and the imaged subject And its standard level cannot be defined Parameter reference the chrominance signal NTSC standard setting CAT1_Byte13_bit0 6 BSTLV 38 h burst a...

Page 61: ...ss than the analog output D range 2 5 To the extent that the D range value is small one might consider increasing the standard AD input level However the standard A D input level 400 mV which is the same level setting used in analog output should be used because even in cases where only digital output is used the same H W and F W as are used in analog output are used with respect to the AE and AWB...

Page 62: ...dress Description Theoretical recommended value RECYGAIN CAT10_Byte8_bit0 7 Digital Y output gain coefficient 0 x1 99 B1 h x1 38 RECRYGAIN CAT10_Byte9_bit0 7 Digital R Y output gain coefficient 0 x3 99 90 h x2 25 RECBYGAIN CAT10_Byte10_bit0 7 Digital B Y output gain coefficient 0 x3 99 90 h x2 25 Note When digital output is used the apparent gain coefficient on the screen may be offset due to fact...

Page 63: ...es where the SS HQ1 system is controlled through an external microcomputer we recommend using that because it includes serial communication specifications which are more efficient than RS 232C For details see 12 4 When Using the External Microcomputer Use the pin settings in the following table on a CXD3172AR which is to be used in RS 232C If you switch SIFSEL be sure to reset the system Table 9 1...

Page 64: ...n speed 19200 bps PARITY NONE DATA bits 8 bit STOP bits 1 bit Handshaking Nothing The speeds listed below can be selected through a parameter as communication speeds This setting is applied after it is written to the EEPROM and a reset is performed Table 9 1 3 Communication Speed Settings Parameter Description 0 h 9600bps BPSSEL CAT12_Byte10_bit0 1 h 19200bps Note that if the communication speed s...

Page 65: ...error occurs an error code is sent to the host after the reception of the valid byte count Fig 9 1 2 Communication Timing When Communication Error Occurs If the received byte count does not change for 15 fields or more then an error code is sent to the host as a Timeout Error after which the state transitions to the reception wait state Fig 9 1 3 Communication Timing When Timeout Error Occurs Firs...

Page 66: ...on format Command Description 1 2 3 4 5 6 29 30 32 CMD 05 h 01 h CAT Byte Data Num 01 h 1F h Register Category specification Read Reply Data Num 1 Read Data CMD Data Num 4 02 h CAT Byte Write Data Register Category specification Write Reply Data Num 1 Write Data CMD 05 h 03 h CAT Byte Data Num 01 h 1F h EEPROM Category specification Read Reply Data Num 1 Read Data CMD 05 h 04 h CAT Byte Data Num 0...

Page 67: ... 0000 h EEPROM Address 02FF h Note Data pertaining to categories 5 22 and 23 are not written to EEPROM so it is not possible to specify 05 h 16 h or 17 h in EEPROM category specification write read commands An error occurs if the specified byte count exceeds the count for a given category in the category specification command codes 01 h 02 h 03 h and 04 h Error codes When a command is received if ...

Page 68: ...on clock is made by frequency dividing the CXD3172AR s encoder clock ECK Therefore communication may not work properly in cases where MODESEL is not set correctly or when the ECK frequency shifts significantly from the recommended value 9 1 7 When Communication is Not Used In order to prevent operation errors in cases where the serial interface is not being used set the pins as shown in Table 9 1 ...

Page 69: ...r details see 12 4 When Using the External Microcomputer 9 2 2 Pin Connections for Serial Communication with Individual ICs Use the pin connections in the following table to connect the DSP with peripheral ICs Table 9 2 1 Serial Communication Pin Connections inside the SS HQ1 system CXD3172AR Signal name Pin No I O Connected IC Signal name Pin No Remarks EEPROM SK 4 CASCK 9 OUT EVR CLK 13 Serial c...

Page 70: ...mended by Sony Note that these settings cannot be customized by the user Serial communication is performed based on each field VD except during communication with the EEPROM Communication with the EEPROM takes place only when a write read command is received The communication sequence and communication start timing for each field are optimally controlled by the firmware so you do not need to worry...

Page 71: ...hich shows the timing for communication with the CXD3172AR in the MB88347L which is recommended by Sony The timing for transmission from the CXD3172AR to the MB88347L varies depending on the particular MB88347L pin Transmissions to A01 to A04 are sent every field while transmissions to A05 to A08 are sent every four fields rotating among them in field increments Table 9 2 2 External EVR Transmissi...

Page 72: ...munication sequence and communication start timing for each field are optimally controlled by the firmware so you do not need to worry about them Note that the sequence and timing cannot be customized by the user Please note that if parameter controls transmission reception and EEPROM access relating to DSP peripheral ICs are performed through RS 232C communication SS HQ1 Control Software or throu...

Page 73: ... pin 88 Note that this frequency is uniquely determined by the DSP firmware and cannot be set by the user Table 9 2 3 Serial Communication Clock Frequency Clock frequency MHz X tal ECK CASCK 27 00000 0 84 28 37500 0 89 28 63636 0 89 35 46895 1 11 37 87500 1 18 38 13986 1 19 External EVR Fig 9 2 3 Communication Protocol External EVR A0 A1 A2 A3 D7 D6 D3 D2 D1 D0 S4 or P3 CSEVR CASCK CASO A0 DUMMY 1...

Page 74: ... Fig 9 2 5 Communication Protocol EEPROM Read COMMAND 1st to 4th bit C7 D7 D6 D0 CSROM CASCK CASO C6 C0 A7 A6 A0 D7 D6 D0 ADDRESS 5th to 8th bit DATA 9th to 32th bit COMMAND 1st to 4th bit C7 XX XX XX CSROM CASCK CASO C6 C0 A7 A6 A0 XX XX XX ADDRESS 5th to 8th bit DATA 9th to 32th bit D7 D6 D0 CASI D7 D6 D0 ...

Page 75: ...13986 10 4 EEPROM initial recognition process The EEPROM is initially recognized based on data written to the EEPROM s 00 h address The following are determined during the initial recognition process 1 Is communication with the EEPROM possible 2 What is the EEPROM type Asahi Kasei or Rohm 3 Are valid data written to the EEPROM Parameter initialization by EEPROM Parameters are initialized as follow...

Page 76: ...5 MODESEL setting does not match the operating mode then the operation may not work properly and communication may fail In such cases it is not possible to write initial value data to the EEPROM Change the port driver MODESEL setting so that it matches the operating mode so that the system runs properly and then write the initial value data to the EEPROM Once the initial value data are written to ...

Page 77: ...ameter setting values can be switched by switches connected to the respective ports even without external communication Sample Application CPUHOLD Assign the 1 bit parameter to P0 Switch OFF Low 0 h ON High 1 h AESPEED Assign the 8 bit parameter to P2 Switch OFF Low FF h ON High 20 h Output Port Driver Each port can be assigned arbitrary 1 bit parameters and changes in the 1 bit parameters can be ...

Page 78: ...Table 10 1 1 Parameters for Specifying Categories P ｎ CAT bit Parameter Input port setting Output port setting 0 1 2 3 4 PnCAT 0 Port driver does not function 1 to 24 Specify the category number 5 21 and 22 Port driver does not function 5 6 7 PnLSB 0 to 7 Specifies LSB of arbitrary parameters Unused Table 10 1 2 Parameters for Specifying Bytes PDR ｎ Byte bit Parameter Input port setting Output por...

Page 79: ...becomes the LSB PnBYTE Byte Number PnBYTE specifies the byte number of the arbitrary parameter to be controlled by the port driver If set to 0 h the port will not function as a port driver It will not function as a port driver if the setting has a nonexistent byte number in the category to be specified PnIOSEL Port I O Selection PnIOSEL sets a port as an input or an output 0 Input port setting 1 O...

Page 80: ...ter is changed as 60 h 3C h by Low High of port input When PnADJ sets it as 8 h F h The coefficient can be selected from 1 125 times to twice The parameter value The value written to EEPROM x PnADJ 1 8 This parameter value is set by high input of port driver When an input port is High the setting value is calculated by multiplying the parameter value written to EEPROM by the coefficient of the fol...

Page 81: ...nt of an operation result is rounded off Overflow Processing If the calculation results exceed the specified bit width data is incorporated that is within the range of the bit width from the specified LSB Thus complete the settings so that the calculation results do not exceed the specified bit width PnWID Bit Width PnWID specifies the bit width of the arbitrary parameter to be controlled by the p...

Page 82: ...as 0 h P2WID 0 h PGON is 1 bit parameter Thus P2WID is set as 0 h P2Byte 24h PGON is the parameter of 36th Byte of CAT9 Thus P2Byte is set as 24 h Parameter value is set up by hex decimal Thus it changes into 36 d from 24 h P2IOSEL 0 h P2 is set as an input Thus P2IOSEL is set as 0 h P2CAT 9 h PGON is the parameter of CAT9 Thus P2CAT is set as 9 h P2LSB 3 h LSB of PGON is the 3rd bit Thus P2LSB is...

Page 83: ...te is set as 25 h Parameter value is set up by hex decimal Thus it changes into 36d from 24 h P1IOSEL 0 h P1 is set as an input Thus P1IOSEL is set as 0 h P1CAT 2 h RYGAIN1 is the parameter of CAT2 Thus P1CAT is set as 2 h P1LSB 0 h LSB of RYGAIN1 is the 0th bit Thus P1LSB is set as 0 h 1 The P1ADJ setting The parameter value is 1 5 times of value written to EEPROM Thus use the following formula F...

Page 84: ...r P3Byte 1 h Please set to 1 h because MIRROR is the parameter of 1st Byte of CAT1 P3IOSEL 1 h Please set to 0 h because it is set as an output P3CAT 1 h Please set to 1 h because MIRROR is the parameter of CAT1 P3LSB 4 h Please set to 4 h because LSB of MIRROR is the 4th bit 1 port supports 1bit when you can watch the state of parameter from output port Therefore the ports of number of bits are r...

Page 85: ... means of initial values stored in the CXD3172AR Table 10 1 6 Port Driver Initial Settings When EEPROM is Invalid Port Name Parameter Name Category Description P0 CAT15_Byte1_bit0 P1 CAT15_Byte1_bit1 P2 AWBMODE CAT15_Byte1_bit2 AWB mode settings P3 CRLSON CAT12_Byte11_bit0 Color rolling control mode P4 BLCOFF CAT14_Byte1_bit2 Backlight compensation mode P5 AEREF CAT14_Byte1_bit3 AE parameter refer...

Page 86: ...meter settings PDRHOLD CAT12_Byte5_bit5 1 h CPUHOLD CAT12_Byte5_bit0 1 h The priority ranking of the parameter setting methods is as follows 1 Port driver control 2 External communication control computer external microcontroller and so on 3 EEPROM setting values 4 CXD3172AR register setting values The parameter settings assigned to the port drivers are given priority so note that the settings wri...

Page 87: ...SPEED CAT14_Byte12_bit0 7 AESPEED is set to FF h when the input port P0 is a low AESPEED is set to 20 h when the input port P0 is a High Setting Procedure 1 Set PDR to OFF and set PDRHOLD 1 h 2 Set the port driver initial value when the port input is Low make the initial value FF h 3 Set FF h in AESPEED CAT14_Byte12_bit0 7 4 Set the port P0 setting parameter CAT20 See 10 1 3 Parameter Setting Inst...

Page 88: ...al output is enabled Ports of the port drivers P0 to P15 serve as combined use output ports for digital out signal output VDHD output OPD Window output and external EVR CS signal output As shown in the following table port drivers will be disabled from the settings of parameters YDSEL CAT1_Byte7_bit4 CDSEL CAT1_Byte7_bit5 VHOUT CAT1_Byte11_bit6 UWINDOUT CAT16_Byte8_bit7 and CSEVRSEL CAT12_Byte10_b...

Page 89: ...n PG signal See 12 5 Pattern Generator PG System delay adjustment Black level digital clamping Blemish detection and compensation See 11 2 CCD blemish detection and compensation Mirror See 10 9 Mirror Function System Delay System Delay is to set the signal processing reference points effective video start positions in the DSP If the reference points are off the preceding or following OB pixels may...

Page 90: ... the CXA2096N product specifications Therefore the same DC offset is also added to the effective video signal The processing of removing the DC offset equivalent to the black level from the AD converted effective video signal inside the DSP is called digital clamping Fig 10 2 3 Digital clamping process AD Input Level PBLK CLPOB DRVOUT AGCCONT MAX VRB Blankng PBLK CLPOB DRVOUT VRB Blankng OFFSET Bl...

Page 91: ...f CLMPHOLD CAT12_Byte5_bit3 is 1 then the processing of overwriting BLACKS1 and BLACKS2 is stopped Do not set BLACKS1 and BLACKS2 to port driver input control Reference Information In the digital clamping process the S1 series and S2 series are separately integrated to determine the accurate black levels BLACKS1 and BLACKS2 for each system based on the CCD pixel array Fig 10 2 4 Reference CCD pixe...

Page 92: ...ee 10 8 Suppress Function Gamma curve correction See 10 4 Variable Gamma Function Negative output SETUP level addition High luminance clip White Clip Output delay Y LPF This low pass filter removes the carrier component of the CCD color on chip filter This filter can be bypassed by setting YLPFOFF CAT2_Byte1_bit3 to 1 h Set YLPFOFF to 0 h in order to remove carrier component interference when usin...

Page 93: ...ollows DELVSEL CAT2_ Byte11_bit0 0 h Weak 1 h Strong Negative Output This function black white inverts the Y signal after gamma curve correction Negative output is used when POSNEG CAT2_ Byte10_bit6 is set to 1 h The chroma signal is simultaneously inverted to a complementary color SETUP Level Addition A setup level can be added to the video output pedestal The results are as follows NTSC SETUP CA...

Page 94: ...cription Setting value WCLIP CAT2_Byte9_bit4 6 Clips luminance signal output level 0 h 78 1 h 89 2 h 100 3 h 105 4 h 111 5 h 116 6 h 120 7 h 153 Output Delay The Y signal output can be independently delayed This function can be used to add a delay difference compared to the chroma signal output or sync signal output Table 10 2 4 Y signal output delay parameter Parameter Address Description Setting...

Page 95: ...s about the details of optical LPF In addition it can check more effectively by the following setup 760H system Without external Y LPF DACMODE CAT1_Byte3_bit2 1 h YC separate High resolution processing In SS HQ1 as shown in the following figure the newly generated high frequency horizontal aperture signal is added to a luminosity signal processing system Fig 10 2 7 Aperture Compensation Block and ...

Page 96: ... Block configulation for high resolution signal processing High resolution related parameter High resolution mode can be turned on and off by switching REON CAT2_Byte12_bit3 When this parameter is OFF a high resolution signal is not added Table 10 2 5 High resolution related parameter Parameter Description Settings range REON CAT2_Byte12_bit3 Switches the high resolution mode ON and OFF 0 h High r...

Page 97: ... high frequency gain 0 x0 1 x1 2 x2 3 x4 2 HAPGL CAT2 Byte1_bit6 7 Set the horizontal aperture compensation low frequency gain 0 x0 1 x1 2 2 x1 3 x2 2 Table 10 2 7 Vertical Aperture Compensation Related Parameters Parameter name Description Initial value VAPG CAT2 Byte2_bit0 3 Sets the V aperture compensation gain from x0 0 h to x1 F h A VAPSL CAT2 Byte2_bit4 6 Applies slice to V aperture compensa...

Page 98: ...ption Initial value HLAPG CAT2 Byte4_bit6 7 Highlight aperture compensation total gain setting from x0 0 h to x2 3 h 2 HLAPTHLV CAT2 Byte5_bit4 5 Sets the threshold level of adding highlight aperture compensation 0 50 1 37 5 2 25 3 12 5 3 HLAPPG CAT2 Byte5_bit6 7 Highlight aperture compensation gain side setting from x0 0 h to x1 3 h 3 HLAPMG CAT2 Byte6_bit0 1 Highlight aperture compensation gain ...

Page 99: ...GB Matrix Complementary Color Filter CCD Primary Color Separation Circuit Color signals R G B are extracted from the raw data Mg Ye G Cy of complementary color filter CCD by matrix operation The spectral characteristics of complementary color filter vary with the type of CCD Therefore matrix values that correspond to each CCD are necessary For proper color reproduction and WB operation refer to 6 ...

Page 100: ...R Y and B Y signals can be suppressed while interlocked with AGC gain Please refer to 10 8 Suppress 10 3 2 Complementary Color Pixel Clipping As CCD output becomes saturated the ratio among the four pixels S1R S2R S1B and S2B changes preventing color saturation unevenness from appearing When a clip level is set for each piece of data prior to chroma signal processing the data are clipped to the pa...

Page 101: ... signal may be adjusted Table 10 3 2 Parameters related to highlight edge color compensation function Parameter Description HLEDLEVL CAT2_Byte24_bit0 7 LSB HLEDLEVM CAT2_Byte27_bit0 2 MSB Sets vertical and horizontal detection levels HLEDDL13 CAT2_Byte27_bit4 Operates the color compensation circuit based on horizontal detection in the delay line output after 1 3HD 2 0 h OFF 1 h ON HLEDDL2 CAT2_Byt...

Page 102: ...ers Table 10 3 3 Enabling HUE GAIN control Parameter Description OUTGAIN CAT12_Byte6_bit1 0 h OFF 1 h ON SPRS CAT12_Byte6_bit2 0 h OFF 1 h ON 2 Switch to four quadrant independent control If HUE GAIN control is set to four quadrant simultaneous control set the following parameter to 1 h in order to switch to four quadrant independent control Table 10 3 4 HUE GAIN adjustment parameters Parameter De...

Page 103: ...CAT2_Byte41_bit0 7 Second quadrant R Y Gain adjustment BYGAIN2 CAT2_Byte42_bit0 7 Second quadrant B Y Gain adjustment RYHUE2 CAT2_Byte43_bit0 7 Second quadrant R Y Hue adjustment BYHUE2 CAT2_Byte44_bit0 7 Second quadrant B Y Hue adjustment RYGAIN3 CAT2_Byte45_bit0 7 Third quadrant R Y Gain adjustment BYGAIN3 CAT2_Byte46_bit0 7 Third quadrant B Y Gain adjustment RYHUE3 CAT2_Byte47_bit0 7 Third quad...

Page 104: ...ress Starts Parameter Description CSVTH CAT2_Byte53_bit2 3 0 h Detection at 25 1 h Detection at 44 2 h Detection at 63 3 h Detection at 81 Table 10 3 9 Setting the False Color Suppress Amount when the Luminance Level is Detected Parameter Description CSHLV CAT2_Byte53_bit4 5 0 h No Suppression 1 h Signal suppressed by 50 2 h Signal suppressed by 75 3 h Signal suppressed by 100 Table 10 3 10 Settin...

Page 105: ...me Description Setting Value Applications 0 h User Gamma 0 value saved in EEPROM A fixed such as a factory default setting The category 2 parameter is saved to EEPROM for use GAMSEL CAT12_Byte7_bit0 Gamma curve selection 1 h User Gamma 1 value set through serial communication A temporary curve change used for applications such as camera installation adjustment portable monitor or matching to a use...

Page 106: ...e areas 0 h OFF 1 h ON Parameters for User Gamma 0 which is enabled when GAMSEL 0 h Saved to EEPROM for use CAT2_Byte7_bit0 YGAMSLV Y gamma curve correction compression level selection for low luminance areas 0 h Strong 1 h Weak CAT13_Byte52_bit2 4 UYGAMSEL Y luminance signal variable gamma selection 0 h to 7 h CAT13_Byte52_bit5 7 UYKNEESEL Y luminance signal variable knee selection 0 h to 7 h CAT...

Page 107: ...f standard input together with six different linear areas based on YKNEESEL or UYKNEESEL for higher than AD input 500 mVp p When YGAMSEL or UYGAMSEL is set to 4 h or when YKNEESEL or UYKNEESEL is set to 3 h the gamma comes closes to 0 45 inverse of standard CRT gamma value of 2 2 and the Y output is 100 equivalent to 100 IRE for NTSC with respect to AD input 400 mVp p 100 of standard input With ma...

Page 108: ...r waveform monitor 10 4 3 Y Gamma OFF You can select one of the lines in Fig 10 4 3 Y gamma OFF in order to make the camera side output linear such as for image data processing using digital output or in cases where the receiving monitor has a gamma correction function Fig 10 4 3 Y Gamma OFF When YKNEESEL or UYKNEESEL is set to 6 h or 7 h the curve becomes a Y gamma OFF The line created by setting...

Page 109: ...the SS HQ1 system also has a function for compressing the low areas of the gamma curve Fig 10 4 4 Gamma Curve Compression in Low Luminance Areas S Gamma When YGAMSON or UYGAMSON is set to 1 h the low luminance areas of the Y gamma curve are compressed The compression characteristics vary depending on the selected gamma curve YGAMSEL or UYGAMSEL Note that the compression level can be selected using...

Page 110: ...e CAT2_Byte30_bit3 4 CKNCLIP Chroma knee high region clipping process 0 h to 3 h CAT13_Byte53_bit0 2 UCGAMMA Chroma signal variable gamma selection 0 h to 7 h CAT13_Byte53_bit5 7 UCKNEE Chroma signal variable knee selection 0 h to 7 h CAT13_Byte54_bit0 UCKNEE2 Chroma knee high region correction CKNEE 3 h only 0 h OFF 1 h ON Parameters for User Gamma 1 which is enabled when GAMSEL 1 h Can be update...

Page 111: ...KNEE or UCKNEE is set to 3 h then the result will be the closest to gamma 0 45 the inverse of standard CRT gamma 2 2 and the output level for 100 input level will be 78 400 511 d Note that the input signals for the chroma variable gamma circuit are equivalent to the following Input signal inside DSP CXD3172AR RGB signal after white balance correction Output signal RGB signal before R Y and B Y col...

Page 112: ...h cases CGAMMA or UCGAMMA is disabled The line formed by CGAMMA or UCGAMMA 0 h and CKNEE or UCKNEE 5 h is identical to the line formed by CKNEE or UCKNEE 7 h 10 4 7 Chroma Knee High Region Correction When CKNEE or UCKNEE is set to 3 h and CKNEE2 or UCKNEE2 is set to 1 h the knee area at 150 input level and higher is bent as shown in the following graph Fig 10 4 7 Chroma Knee High Region Correction...

Page 113: ...KNEE Also linked to CKNEE2 1 h UCKNEE2 1 h The output level depends on the CKNEE UCKNEE setting Examples CKNCLIP 1 h CKNEE 3 h CKNEE2 1 h Output is clipped to 100 chroma knee output at 300 input and higher CKNCLIP 1 h CKNEE 4 h Output is clipped to 160 chroma knee output at 300 input and higher CKNCLIP 3 h CKNEE 4 h Output is clipped to 120 chroma knee output at 200 input and higher Note These out...

Page 114: ...ists of a 15x15 grid extending in the horizontal and vertical directions The overall area is determined by setting the window starting position and the size of a single grid It is divided into five areas WINDOW0 WINDOW1 WINDOW2 WINDOW3 and WINDOW4 Different weightings can be set for each area When the WINDOW4 starting grid and grid length are setting the positions and sizes of WINDOW0 WINDOW1 WIND...

Page 115: ...on WINDOW4 vertical grid width grid When the mirror function is used the detection window is set with respect to the horizontally flipped video signal The window starting position is in the upper left corner after the flip Adjust the horizontal position of the detection window using the mirror horizontal start position parameters UOPDWHSTM and UOPDW4HSTM in order to link the mirror function and de...

Page 116: ...bit1 4 Selects detection window to be displayed on monitor 1 h WINDOW 0 2 h WINDOW 1 3 h WINDOW 2 4 h WINDOW 3 5 h WINDOW 4 7 9h AWB integration area display 0 6 A F h NONE UWINDOUT CAT16_Byte8_bit7 When set to 1 h outputs High from P4 pin 96 for the WINDOW period set in UOPDDISP Port 4 driver control is turned off for the duration of UWINDOUT 1 h Detection window display UOPDDISP also permits the...

Page 117: ... gain RETURN Fixed shutter speed Calculation of subject exposure Fixed gain Processing is branched in modes accepting from DIP switches or serial communication input Shutter speed and AGC gain are obtained from the subject exposure In AE mode the subject exposure is calculated from the integral value of each OPD window A judgment regarding backlight conditions is made based on the data from OPD an...

Page 118: ...AR Pins 96 to 99 AEME CXD3172AR Pin 76 and AESHUT CXD3172AR Pin 77 2 For serial communication switching is done by setting PDRHOLD 1 h and using the parameters in the table Parameters and DIP Switches These settings combinations are equivalent DIP setting Low Serial setting 0 h and DIP setting High Serial setting 1 h The parameters are explained in the next section Table 10 6 1 Parameters and DIP ...

Page 119: ...AE Mode Parameters Parameter Description Settings range BLCOFF CAT14_Byte1_bit2 Deactivates backlight compensation 1 h No backlight compensation AEREF CAT14_Byte1_bit3 Enables switching and setting the AE convergence level At 1 h the setting value of AEUSR CAT14_Byte13_bit0 to 7 is applied 0 h 100 IRE 1 h AEUSR setting AGCMAX CAT14_Byte1_bit4 Enables switching two types of AGC maximum gain 0 h AGC...

Page 120: ... 3 Electronic Shutter Speed Setting Parameters Parameter Description Settings range AESHUT CAT14_Byte1_bit6 AE shutter mode ON OFF 0 h OFF 1 h ON SHUTMAX CAT14_Byte17_bit0 7 Electronic shutter speed maximum value 0 h to FF h SHUTMIN CAT14_Byte18_bit0 7 Electronic shutter speed minimum value 0 h to FF h SHTSEL CAT14_Byte3_bit2 4 Electronic shutter speed selector 0 h to 7 h LLFLC CAT14_Byte2_bit1 Lo...

Page 121: ... 115 Table 10 6 5 Example of Setting the Shutter Speed PAL LLFLC SHUTMAX SHUTMIN SHTSEL Shutter Speed sec 0 FF 0 0 1 50 1 FF 0 0 1 120 0 BD 0 2 1 250 0 B4 0 3 1 500 0 B0 0 4 1 1 000 1 BB 0 4 1 2 000 0 CE 0 5 1 4 000 1 A8 0 7 1 10 000 0 FF 0 7 1 100 000 ...

Page 122: ...see 10 5 OPD Window Setting and Display Fig 10 6 2 AE Detection Windows of OPD Note If set so that the size of window 4 is extremely small and the weighting of windows 0 to 3 is 0 it will cause rounding errors from the internal calculation Care should be taken because this worsens the accuracy of AE operation resulting in an effect like oscillation Table 10 6 6 Detection Windows Weighting Values C...

Page 123: ...t4 and AGCFLOF CAT14_Byte2_Bit3 are all 0 h the general range around the speed selected for the electronic shutter fixed method NTSC 1 100 sec PAL 1 120 sec is a reference point For shutter control faster than this compensation control is performed through shutter speed modulation flickerless function Control at lower speeds is performed through AGC gain modulation flickerless control LLFLC Mode L...

Page 124: ... the threshold value for AE operation to stop after it is in effect 0 h none to FF h maximum Notes Table 10 6 10 AEHYST AEHYST AE HYSTeresis Category CAT14_Byte10_bit0 7 8bit Outline The threshold value at which AE control starts can be set Conditions AEHYST 0 AEWAIT 0 AEHYST AESTAB Available settings range 00 h to FF h 8bit Initial value 0 h Description Specifies the dead zone relevant to fluctua...

Page 125: ...line The hysteresis counter can be set Conditions AEHYST 0 AEWAIT 0 AEHYST AESTAB Available settings range 00 h to FF h 8bit Initial value 0 h Description The greater the value the less responsive AE is with respect to momentary fluctuations of the subject s luminance level The smaller the value the more responsive the reaction Notes ...

Page 126: ...EVR1 The AE operation is performed using AGC control based on the microcontroller s AE and the mechanical iris inside the external lens Example configuration of mechanical iris using IRISVCNT The CCDLEVEL signal of CXA2096N is used as the video signal The amplitude of this signal can be controlled by VCA which is controlled by the IRISVCNT voltage after level adjustment by a pre amp circuit This m...

Page 127: ...2 EVR value when mechanical iris backlight compensation is 6dB 0 h FF h VCA0 CAT14_Byte23 EVR value when mechanical iris backlight compensation is 0dB 0 h FF h VCAP6 CAT14_Byte24 EVR value when mechanical iris backlight compensation is 6dB 0 h FF h VCAP12 CAT14_Byte25 EVR value when mechanical iris backlight compensation is 12dB 0 h FF h Fig 10 6 4 Example VCA settings control range 12dB to 0dB No...

Page 128: ...same as for AESHUT mode as described above Additionally the gain for AGC can be set with AEREF and BLCOFF See the Table 10 6 13 AGC Gain in ME Mode The gain can be selected with AGCMAXL as selected in AGCMAX or from four scale values equally dispersed between AGCMAXH and AGCMIN Table 10 6 13 AGC Gain in ME Mode Parameter Combinations of BLCOFF and AEREF BLCOFF CAT14_Byte1_bit2 0 1 0 1 AEREF CAT14_...

Page 129: ... h can be set as shown in the figure Correspondence of AGCMIN AGCMAXL AGCMAXH and AGC Gain Notes Valid when AGCMAX is 0 h Set it at or above the value of AGCMIN Table 10 6 15 AGCMAXH AGCMAXH ae AGC MAXimum gain High Category CAT14_Byte16_bit0 7 8bit Outline Enables the AGC maximum gain to be set Conditions AGCMAX 1 h setting Available settings range 00 h to FF h 8bit Initial value FF h Description...

Page 130: ...mum gain to be set Conditions Available settings range 00 h to FF h 8bit Initial value 28 h Description The minimum value limiter of AGC can be set as shown in the figure Correspondence of AGCMIN AGCMAXL AGCMAXH and AGC Gain Notes Fig 10 6 5 Correspondence of AGCMIN AGCMAXL AGCMAXH and AGC Gain 0 10 20 30 0 20 40 60 80 A0 C0 E0 AGCMIN AGCMAXL AGCMAXH h AGC Gain dB ...

Page 131: ... 1 h USR Available settings range 00 h to FF h 8bit Initial value 0 h 60IRE Description The white video level when shooting a test chart can be set as shown in the table AEUSR and AE Convergence Values Notes Table 10 6 18 AEUSR and AE Convergence Values AEUSR IRE 00 h Approx 60 01 65 02 70 03 75 04 80 05 85 06 90 07 95 08 100 09 105 0A 110 0B 115 0C 120 0D 400mV adjustment reference for AGCMIN 0E ...

Page 132: ...me is selected Next operations are performed using the data from the OPD 4 The detection data from the OPD is converted to R G B G and R B G R B 2G G format 5 In ATW mode after performing white detection the operation frame is judged and operation shifts to convergence processing Fig 10 7 1 AWB Flow Chart START Modeselection Fixedvaluemode Datainput R G B Operationframe selrction R G B G R B G R B...

Page 133: ...WB amplifire Please be sure to carry out pre white balance adjustment before using ATW See Pre WB adjustment mode under 11 Description of Operation of Each Mode for the pre white balance adjustment method Push Push mode has no operation frame or other limitations and performs correction so that the R G B evaluation value is always 1 1 1 In addition the convergence speed can be adjusted by ALLSTEP ...

Page 134: ...0 7 2 Trace Curve for Manual White Balance image In MWB mode the parameters controlled through key operations SFTUP SFTDWN are WBR and WBB in Table 10 7 4 When the key is released or set to 0 h after making adjustments using the SFTUP or SFTDWN key the gain at that time is saved to a parameter in Table 10 7 5 and saved to EEPROM To start up using the gain value written to EEPROM perform a reset st...

Page 135: ...tion before the mode transition Also when shifting to hold mode from push mode the gain value at that time is stored in the EEPROM so push lock mode can be realized by using hold mode in combination with push mode In addition conventional push lock mode and trigger system push lock mode can be switched by switching the parameter AWBTRG CAT15_Byte2_bit1 1 Conventional push lock mode AWBTRG 0 h Oper...

Page 136: ...r R gain 2 3200K 00 h FF h WBUSRB2 CAT15_Byte38_bit0 7 User B gain 2 3200K 00 h FF h WBUSRR3 CAT15_Byte39_bit0 7 User R gain 3 4200K 00 h FF h WBUSRB3 CAT15_Byte40_bit0 7 User B gain 3 4200K 00 h FF h WBUSRR4 CAT15_Byte41_bit0 7 User R gain 4 6300K 00 h FF h WBUSRB4 CAT15_Byte42_bit0 7 User B gain 4 6300K 00 h FF h AWB monitor mode This mode outputs the white balance gain value during AWB operatio...

Page 137: ...frame canceled less than approximately 2000 K more than approximately 18000 K Table 10 7 9 Operation frame setting parameters Parameter Description Settings range ATWFRAMOF CAT15_Byte3_bit0 ON OFF setting for ATW operation frames all frames 1 to 3 0 h ON 1 h All Cancel ATWFRM1OF CAT15_Byte3_bit1 ON OFF setting for ATW operation frame type 1 0 h ON 1 h Cancel ATWFRM2OF CAT15_Byte3_bit2 ON OFF setti...

Page 138: ...nse characteristics and the convergence speed Table 10 7 11 UWBYREFL UWBYREFL Category CAT15_Byte28_bit0 7 8bit Outline Sets the minimum value on the medium luminance side of the integral range for luminance specific integration Conditions AWBMODE 0 h Available settings range 0 h FF h 8bit Initial value 4 h Description When AWBSEPOF 0 h The integral range is fixed to UWBYREFL to UWBYREFH When AWBS...

Page 139: ... the optimum region is selected for ATW control Notes Please set value like UWBYREF INTSLICE UWBYREFH Table 10 7 13 UWBYREFH UWBYREFH Category CAT15_Byte30_bit0 7 8bit Outline Sets the maximum value on the high luminance side of the integral range for luminance specific integration Conditions AWBMODE 0 h Available settings range 0 h FF h 8bit Initial value 0 h Description When AWBSEPOF 0 h The int...

Page 140: ... Table 10 7 15 AWBSPED AWBSPED AWB SPEeD Category CAT15_Byte5_bit0 7 8bit Outline Sets the ATW control speed Conditions Available settings range 0 h FF h 8bit Initial value 2 h Description 0 h Maximum speed FF h Minimum speed Notes This parameter affects both the ATW response characteristics and the convergence speed Table 10 7 16 WBDLY WBDLY White Balance DeLaY Category CAT15_Byte6_bit0 7 8bit Ou...

Page 141: ...oint shift modes of auto discrimination mode and select 1 point mode Auto discrimination mode automatically discriminates the convergence point position and controls the gain In this mode the convergence point shift can be set in four directions In addition select 1 point mode shifts the convergence point to an optional preset point The convergence point shift mode is switched by AWBSFT CAT15_Byte...

Page 142: ...he G R B and Mg convergence points can be shifted in an optional direction Notes When this value is too large convergence operation is not performed This parameter is only valid in ATW mode Table 10 7 20 ATWRSFT2 ATWBSFT2 ATWRSFT2 ATWBSFT2 ATW Red ShiFT2 ATW Blue ShiFT2 Category CAT15_Byte8 9 10 11_bit0 7 8 bits each Outline ATW convergence point shift 2 Sets the shift amount in the R and B direct...

Page 143: ...agenta DeadBAND Green Category CAT15_Byte15 16 17 18_bit0 7 8 bits each Outline Sets the dead band width in the R B Mg and G directions for the convergence start judgment Conditions Available settings range 0 h FF h 8bit Initial value 12 h 12 h 12 h 12 h Description The dead band can be adjusted in the four directions of R B Mg and G These parameters are the dead band widths used to make the next ...

Page 144: ...t of each window of OPD Conditions AWBWON 1 h Available settings range 0 h 3 h 2bit Initial value 2 h 2 h 2 h 2 h 2 h Description 0 h x0 1 h x1 16 2 h x1 4 3 h x1 Notes When AWBWON CAT4_Byte 5_bit 2 1 h windows with a weighting of x0 are not displayed on the monitor Table 10 7 24 Detection frame display parameters Parameter Description Remarks UOPDDISP CAT16_Byte8_bit1 4 Selects the detection fram...

Page 145: ...tment of response speed Dead band width for determination of convergence start Convergence point shift Select 1 point only Table 10 7 25 CRLESSON CRLESSON Color Rolling LESS ON Category CAT12_Byte11_bit0 1bit Outline ON OFF setting for anti color rolling mode Conditions Available settings range 0 h 1 h 1bit Initial value 0 h Description 0 h OFF 1 h ON When this is ON the two anti color rolling cou...

Page 146: ...the SS HQ1 also has operation frames for color rollingless AWB mode Two types of operation frames can be set and turned on and off independently Table 10 7 28 CRFRMOFF CRFRMOFF anti Color Rolling FRaMe OFF Category CAT15_Byte44_bit0 1bit Outline ON OFF setting for color rollingless AWB operation frames Conditions CRLESSON 1 h Available settings range 0 h 1 h 1bit Initial value 0 h Description 0 h ...

Page 147: ... Frame 1 is turned off by CRFRM1OFF Frame 2 is turned off by CRFRM2OFF See Fig 10 7 5 Operation frame of Color rollingless for frame 1 and frame 2 Notes Table 10 7 30 CRRGMAXL CRRGMAXH CRRGMINL CRRGMINH CRRGMAXL CRRGMAXH CRRGMINL CRRGMINH Category CAT15_Byte45 46 47 48_bit0 7 8 bit each Outline Sets the color rollingless AWB operation frames Conditions CRLESSON 1 h CRFRMOFF 0 h Available settings ...

Page 148: ... SS HQ1 Application Notes Ver 1 0 0 January 7 2005 142 Fig 10 7 5 Operation frame of Color rollingless R B G R B 2G G R G B G Frame 1 Frame 2 Final Operation frame ...

Page 149: ...tart AGCCNT end AGCCNT minimum level are changed by using the following parameters CSPRSTA Chroma suppress start AGCCNT CSPREND Chroma suppress end AGCCNT CSPRMIN Chroma suppress minimum level Table 10 8 2 CSPRSTA CSPRSTA Chroma SuPpRess STArt level Category CAT13_Byte19_bit0 7 8bit Outline Chroma suppress start AGCCNT Available setting range 00 h to FF h 8bit Initial value A0 h Description Notes ...

Page 150: ...ess minimum level Available setting range 00 h to FF h 8bit Initial value 8A h Description 00 h Complete suppress FF h No suppress Notes Table 10 8 5 CSPR CSPR Chroma SuPpRess Category CAT12_Byte6_bit4 1bit Outline Switches the chroma suppress ON and OFF Conditions SPRS 1 h Available setting range 0 h 1 h 1bit Initial value 1 h Description Notes Enabled when SPRS 1 h ...

Page 151: ...bit0 7 8bit Outline Aperture correction suppress start AGCCNT Available setting range 00 h to FF h 8bit Initial value A0 h Description Notes Don t set a value larger than ASPREND Table10 8 7 ASPREND ASPREND Apcon SuPpRess END level Category CAT13_Byte17_ bit0 7 8bit Outline Aperture correction suppress end AGCCNT Available setting range 00 h to FF h 8bit Initial value D0 h Description Notes Don t ...

Page 152: ...bit3 1bit Outline Switches the apcon suppress ON and OFF Conditions SPRS 1 h Available setting range 0 h 1 h 1bit Initial value 1 h Description Notes Enabled when SPRS 1 h Fig 10 8 1 Suppress Characteristics Diagram Suppress ratio AGC Start level 100 FF h Suppress Minimum level End level Present AGC Suppress level ...

Page 153: ...on The video signal which reversed right and left as shown in the following figure can be outputted by using the mirror function Notes It has no top bottom reversal function Fig 10 9 1 Outline The mirror setting procedure is as follows MIRROR CAT1_Byte1_bit4 0h Normal image 1h Mirror image Normal image Mirror image ...

Page 154: ...9_Byte9 16 Mask horizontal direction end position 1 step 4 MCK MSKnVSET CAT9_Byte17 24 Mask vertical direction start position 1 step 4 lines MSKnVRST CAT9_Byte25 32 Mask vertical direction end position 1 step 4 lines MSKBYLV CAT9_Byte33 Color B Y setting MSKRYLV CAT9_Byte34 Color R Y setting MSKYLV CAT9_Byte35 36 Luminance level MSKON CAT9_Byte36_bit2 Show mask 0 OFF 1 ON MSKHLD CAT9_Byte36_bit3 0...

Page 155: ...f MSKnHSET and MSKnVSET to the entire mask set the 0th hold function MSKHLD CAT9_Byte36_bit3 to ON 1h Accordingly during 0th hold execution the settings of MSKBYLV MSKRYLV and MSKYLV are disabled Activate 0th hold by setting MSKHLD to 1h If there are overlapping masks the mask with the smaller number is given priority as shown in the following figure In this case the colors of MASK0 and MASK1 are ...

Page 156: ...ameter values at 7h or higher If they are set under 7h the mask start position during 0th hold would exceed the period of the effective video signal so the held color would be incorrectly displayed 5 Set all MSKnHSET parameter values at 2h or higher If they are set under 2h the mask is not displayed 6 With 0th hold shooting in dark conditions when the iris is closed for example may make the masked...

Page 157: ...ideo output to the equivalent of 100 IRE when the A D input is 400 mVp p because the D range is 250 At the CCD standard output of 250 mVp p the A D input must be 400 mVp p but the actual AGC gain characteristic CXA2069N varies in each case This adjustment sets the minimum AGC gain required to absorb variations in the AGC gain characteristic CXA2069N and set the A D input to 400 mVp p when the CCD ...

Page 158: ...roximately 3200K to obtain a color temperature of approximately 2500K Confirm the convergence 5 After setting PREWBMODE CAT12_Byte3 to 3 h apply a color temperature conversion filter to the light source approximately 3200K to obtain a color temperature of approximately 9500K Confirm the convergence 6 After setting PREWBMODE CAT12_Byte3 to 0 remove a color temperature conversion filter 7 Write the ...

Page 159: ...LMDETFIN CAT12_Byte4_bit6 End flag of the static blemish detection BLMDETAGC CAT21_Byte1 The setting value of AGC gain operating the static blemish detection OPSHBLMDET CAT21_Byte2_bit1 The automatic static blemish detection 0 OFF 1 ON The static blemish detection procedure is shown below Manual mode 1 Shade CCD by closing the iris of the lens 2 The value of the AGC gain under blemish detection is...

Page 160: ...g the iris of the lens 1 Normal static detection and compensation mode OPSHBLMDET 0 h 1 Set OPSHBLMDET to 0 h OPSHBLMDET 0 h sets normal static detection and compensation mode 2 Set the blemish compensation function to ON DEFON 1 h 3 Set the blemish detection range See 11 2 CCD blemish detection and compensation 4 Set the detection threshold levels in DETREFL M and LARGEREFL M 5 In BLMDETAGC set t...

Page 161: ... AWBOUT1 CAT23_Byte1 R gain WBR CAT4_Byte1 AWBOUT2 CAT23_Byte2 G gain WBG CAT4_Byte2 AWBOUT3 CAT23_Byte3 B gain WBB CAT4_Byte3 AWBOUT4 CAT23_Byte4 0 Fixed AWB Co process Mode Set ADJMODE to 32 h to enter AWB co process mode In AWB co process mode the OPD evaluation values for AWB controls are output in AWBOUT1 4 See Table 11 1 7 Outputs in Co process Mode for the individual output values Table 11 ...

Page 162: ... and corrects blemishes in order of blemish level starting with the highest blemish level It can detect and correct 32 blemishes 11 2 1 CCD blemish detection method types Static blemish detection Static detection A blemish is recognized by static detection when a target pixel is more than a fixed level to a black level while the CCD is shielded from light Dynamic blemish detection Dynamic detectio...

Page 163: ...tion of the blemish detection area HWIDTHL CAT11_Byte15_bit0 7 LSB HWIDTHM CAT11_Byte17_bit4 5 MSB Used to set the horizontal width of the blemish detection area VWIDTHL CAT11_Byte16_bit0 7 LSB VWIDTHM CAT11_Byte17_bit6 7 MSB Used to set the vertical width of the blemish detection area These parameters can be used for both static detection and dynamic detection Fig 11 2 1 Detection Area Setting Di...

Page 164: ...tatic detection operation Fig 11 2 2 Static detection operation Compensation operation Blemish pixels are corrected by replacing them with the average value of two pixels of the same color filter which are adjacent in the horizontal direction The results of blemish detection and compensation appear in Table 11 2 6 Parameters for storing blemish detection results Blemish Level Blemish Pixel and Cir...

Page 165: ...witching blemish detection modes Parameter Description LARGEON CAT11_Byte1_bit3 0 h Normal blemish detection mode 1 h Large blemish detection mode These parameters can be used for both static detection and dynamic detection Detection threshold level settings These parameters are used to set the blemish threshold level and the large blemish threshold level Pixels exceeding the levels set in these p...

Page 166: ...CNTn Vertical address of blemish HCNTn Horizontal address of blemish DETLVn CAT11_Byte20 147 Blemish level 10bit data n 0 31 These parameters can be used for both static detection and dynamic detection Blemish address resetting This parameter is used to reset the values of parameters storing blemish detection results all values are set to 00 h Note that if blemish detection results are written to ...

Page 167: ...h 32 corrections These parameters can be used for both static detection and dynamic detection Accumulation time setting This parameter sets the accumulation time number of accumulated frames for static detection For low level blemishes the blemish level will gradually increase as the accumulation time is increased When the blemish level exceeds the set threshold level a blemish is recognized and d...

Page 168: ...AGC to set the AGC gain to be applied during blemish detection See Table 11 2 10 6 Set ADJMODE to 22 h ADJMODE 22 h Starts blemish detection and compensation See Table 11 2 10 7 Read the parameters If BLMDETFIN 1 h detection and compensation are terminated See Table 11 2 10 8 The values of Bytes 20 147 in CAT11 BLMDET1 parameters for storing detection results are written to EEPROM 9 Set ADJMODE to...

Page 169: ...use the blemish level and accumulation time are proportionate to each other Accumulation time 2field DETACCT 2 2 field increments Next in order to transfer the CCD output to the CXD3172AR the CXA2096N performs sample hold and performs AGC processing The output from the CXA2096N is A D converted inside the CXD3172AR In order to perform blemish detection by Z1 block DETREFL M 10bit is compared with ...

Page 170: ... output is increased to improve detection precision For example if DETACCT 32 20h output equivalent to AGC30dB can be obtained and detection can be performed at the 15 6mV 511 gradient without degrading the S N ratio However please set DETACCT to become Det_Max_value 1000 mV black offset mV 1000 mV x1023 3FF h Fig 11 2 4 CCD Blemish level accumulation time and DETREF Black offset value 3FF h 1023 ...

Page 171: ... false detection may take place in dynamic detection However there is also a function for releasing such false blemishes With this function false blemishes up to a level set by the user can be released The diagram below shows an image of the dynamic detection operation Determination data are the target pixel s level and the levels of the peripheral horizontal and vertical pixels In reality CCD per...

Page 172: ...tection operation 3 If a blemish address held in detection operation 2 matches the address from N fields earlier then a blemish is recognized The number of fields N can be set using the parameter FLDWAIT Compensation operation Blemish pixels are corrected by replacing them with the average value of two pixels of the same color filter which are adjacent in the horizontal direction same as for stati...

Page 173: ...7 0 h Turns dynamic detection function OFF 1 h Turns dynamic detection function ON default Set this parameter to 1 h even if you do not plan on using the dynamic detection function Detection mode settings This parameter is used to switch between normal blemish detection mode and large blemish detection mode Normal blemish detection mode is detected to one blemish pixel In large blemish detection m...

Page 174: ...EFL M be sure to set a value that is greater than the DETREFL M value DETREFL M LARGREFL M Blemish detection results The blemish detection results type level address are written to these parameters Blemish detection results for a total of 32 blemishes may be written If there are fewer than 32 blemishes e g if there are just two blemishes the other parameters are left at their initial values and ar...

Page 175: ...s is always 32 However the number of corrections is set using the following parameter Table 11 2 17 Parameter for setting the number of blemish corrections Parameter Description DEFNUM CAT11_Byte3_bit2 6 Correction count setting 0 h 1 correction 1F h 32 corrections These parameters can be used for both static detection and dynamic detection Dynamic detection wait field count setting In dynamic det...

Page 176: ...ls are not judged 3 h Three of the ten peripheral pixels are not judged 4 h Eight pixels above below left right 5 h One of the eight pixels above below left right is not judged 6 h Four pixels above below left right 7 h Four pixels in horizontal direction Fig 11 2 7 Layout of target pixel and peripheral pixels Blemish releasing function ON OFF This parameter is used to turn ON OFF the function for...

Page 177: ...g function is used as shown in the diagram below held blemishes which have once exceeded the threshold level DETREFL M can be released if they fall below the blemish releasing level DELREFL M due to imaging subject conditions Fig 11 2 8 Overview of blemish releasing function Cancel Circumference Pixel Large Blemish level LARGEREFL M Circumference Pixel Detection level DETREFL M Blemish release lev...

Page 178: ... See Table 11 2 20 4 Set the number of detection wait fields See Table 11 2 18 5 Set the blemish reference dark level DARKREFL M See Table 11 2 19 6 Use DETREFL M and LARGEREFL M to set the detection threshold levels See Table 11 2 14 7 Turn the dynamic detection function ON DYNDETON 1 h See Table 11 2 12 8 Turn the blemish compensation function ON DEFON 1 h See Table 11 2 11 To change the detecti...

Page 179: ...y be used with both static detection and dynamic detection Related parameters False blemish generating function False blemishes can be detected and corrected just like CCD blemishes Use this function to check the operations of the blemish detection and correction function Table 11 2 23 Parameters false blemishes Parameter Description DEFPG CAT11_Byte1_bit0 0 h No false blemishes 1 h Generate false...

Page 180: ...n in Table 11 3 2 a setting value is changed and the amount of delay can be adjusted Please refer to Fig 11 3 1about the situation of change Table 11 3 1 Adjusting parameter of delay Parameter Description DEH1 CAT6_Byte9_bit0 3 Adjustment of H1delay DEH2 CAT6_Byte9_bit4 7 Adjustment of H2delay DERG CAT6_Byte10_bit0 3 Adjustment of RG delay DESHP CAT6_Byte10_bit4 7 Adjustment of XSHP delay DESHD CA...

Page 181: ... Please refer to Fig 11 3 2 about the situation of change Table 11 3 3 Adjusting parameter of duty Parameter Description DUH1 CAT6_Byte12_bit0 3 Adjustment of H1duty DUH2 CAT6_Byte12_bit4 7 Adjustment of H2duty DURG CAT6_Byte13_bit0 3 Adjustment of RG duty DUSHP CAT6_Byte13_bit4 7 Adjustment of XSHP duty DUSHD CAT6_Byte14_bit0 3 Adjustment of XSHD duty DURS CAT6_Byte14_bit4 7 Adjustment of XRS dut...

Page 182: ...e Amount of adjustment ns Changing point 0 h 0 1 h 1 2 h 2 3 h 3 4 h 4 5 h 5 6 h 6 7 h 7 Falling edge 8 h 0 9 h 1 A h 2 B h 3 C h 4 D h 5 E h 6 F h 7 Rising edge The values shown in table are rough data These values are not guaranteed Fig 11 3 2 Adjustment of duty Setting value 0 h 7 ｈ Setting value 8 h Ｆ ｈ ...

Page 183: ...n the overshoot and the undershoot may appears in TG waveform Please adjust drive ability if you need Table 11 3 5 Drive ability adjustment parameter Parameter Description DRBH1 CAT6_Byte15_bit4 6 Adjustment of H1 drive ability DRBH2 CAT6_Byte16_bit0 2 Adjustment of H2 drive ability DRBRG CAT6_Byte16_bit3 5 Adjustment of RG drive ability DRBSHP CAT6_Byte17_bit0 2 Adjustment of XSHP drive ability D...

Page 184: ... to be used and the specifications of CXD3172AR These phases affect quality of image Therefore it is careful of the phase relation shown in Fig 11 3 4 and we recommend you to confirm by the picture finally Fig 11 3 4 CCDOUT and TG waveform timing image This figure is an image Please refer to this figure when you adjust the phase of TG H2 H1 RG CCDOUT XSHP XSHD XRS ...

Page 185: ...ut at 1 2 the encoder clock ECK rate 13 5MHz output is not supported Sync signal The horizontal sync signal DHD is output through the S0 pin CXD3172AR pin 44 The vertical sync signal DVD is output through the S1 pin CXD3172AR pin 46 The RYBY judgment signal NRYBY is output through the S3 pin CXD3172AR pin 48 ITU REC656 compliant output The chroma signal luminance signal blanking signal and TRC are...

Page 186: ...T1_Byte7_bit5 Port 0 7 pin setting switching 0 h Port driver 1 h C digital signal output S0IN CAT1_Byte7_bit6 S0 pin I O switching 1 0 h DHD output 1 h VRI input S1IN CAT1_Byte7_bit7 S1 pin I O switching 1 0 h DVD output 1 h HRI input S3SEL CAT8_Byte8_bit3 5 S3 pin I O switching 1 0 h DHD 1 h DVD 2 h HD 3 h VD 4 h NRYBY color judgment signal 5 h TEST signal 6 h FLD 7 h Analog shift FSC input BLCKL...

Page 187: ... of luminance output can be varied in the range of 0 h to 1F h using BLCKLV Note that the Y signal high luminance direction range also changes together with the black level The recommended setting is 10 h Digital Output ITU Rec Luminance Output 16 Black level 1 Lower Limit 254 Upper Limit 255 0 Digital Output Straight Luminance Output RECOUT 0 h RECOUT 1 h ...

Page 188: ...EC Parameter REC601 REC656 REC601 REC656 DIFON CAT10_Byte14_bit7 1 h 1 h 1 h 1 h RECOUT CAT10_Byte1_bit0 0 h 0 h 1 h 1 h DIFOUT CAT10_Byte1_bit2 0 h 1 h 0 h 1 h YDSEL CAT1_Byte7_bit4 1 h 1 h 1 h 1 h CDSEL CAT1_Byte7_bit5 1 h 0 h 1 h 0 h BLKCKLV CAT1_Byte1_bit3 7 10 h 10 h The BLKCKLV shown is the recommended value 240 100 Color Bar 16 100 Color Bar 1 Lower Limit 254 Upper Limit 255 0 144 100 Color...

Page 189: ...g period H 0 SAV Start of Active Video H 1 EAV End of Active Video P0 P3 Error correction bits The following table summarizes the serial settings related to TRC settings Table 12 1 6 Serial Settings Related to TRC Output Parameter Description EAVSTAL CAT10_Byte2_bit0 7 LSB EAVSTAM CAT10_Byte3_bit0 2 MSB Variable EAV start position setting Variable value 1 h 1dck SAVSTAL CAT10_Byte4_bit0 7 LSB SAVS...

Page 190: ...t be output Fig 12 1 3 ITU REC656 Relationships Between DCK DHD and Output Data SAV and EAV maximum values and recommended settings for each operation mode Table 12 1 7 SAV and EAV maximum values and recommended settings for each operation mod Recommended value TV system CCD Type Operation mode MODESEL Maximum setting EAVSTAL M SAVSTAL M 510H 0 h 4BB h 0 h CF h NTSC 760H 6 h 71B h 0 h 118 h 510H 3...

Page 191: ... 1 2 3 4 5 6 7 8 9 17 18 19 20 261 262 Field1 ODD Field2 EVEN line4 line5 line18 line19 line20 line21 line262 line263 line264 line265 Line262 F 0 line266 line267 line280 line281 line282 line283 line524 line525 line1 line2 line3 Line263 F 1 Line17 V 1 Line243 V 0 Line16 V 1 Line244 V 0 The line number of an analog composite signal Line3 V 1 Line2 V 1 V blanking 19line V blanking 19line TRC code 0 1...

Page 192: ... Line2 V 1 Line2 V 1 V blanking 24line V blanking 25line 0 1 2 3 4 5 6 7 8 9 23 24 25 26 310 311 312 0 1 2 3 4 5 6 7 8 9 23 24 25 26 311 312 EAV DA h SAV C7 h EAV F1 h SAV EC h EAV B6 h SAV AB h EAV 9D h SAV 80 h EAV 9D h SAV 80 h EAV B6 h SAV AB h EAV F1 h SAV EC h EAV DA h SAV C7 h DHD DVD DFLD Internal signal V counter Internal signal TRC_F Analog ODD Field Digital Field 1 TRC_V The line number...

Page 193: ...7 2005 187 Table 12 1 8 Blanking Parameter Recommended Values Recommended value Parameter NTSC PAL FLD1FSTA CAT10_Byte6_bit0 2 3 h 3 h FLD1VSTA CAT10_Byte6_bit3 7 12 h 18 h FLD2FSTA CAT10_Byte7_bit0 2 3 h 2 h FLD2VSTA CAT10_Byte7_bit3 7 13 h 18 h ...

Page 194: ...ection and the PLL operation is performed in the horizontal direction VSL D In this mode the camera s vertical and horizontal phases are synchronized to an external digital sync signal The reset operation is performed in the vertical direction and the PLL operation is performed in the horizontal direction VBS lock mode VBSL In this mode the camera s vertical horizontal and subcarrier phases are sy...

Page 195: ... is input through the designated pin Based on this result the external synchronization mode is switched automatically see Table 12 2 3 In addition if the parameters set in Table 12 2 4 are set then detection will be disabled even if an external signal is input to the designated pin Table 12 2 2 Detection flag parameters Input pin Parameter Description S1 46pin EXHDET CAT22_Byte1_bit0 EXT HD input ...

Page 196: ... S F h VS lock mode VSL D Enabled when ATMODEON 0 h SGMODE controlled parameters The values of some parameters are controlled automatically based on SGMODE through F W control in order to facilitate external synchronization mode switching The following table shows the relationships between the SGMODE controlled parameters and values The parameters in Table 12 2 6 set the synchronization signal I O...

Page 197: ...hows the relationships between these parameters and SGMODE Table 12 2 8 SGMODE controlled parameters parameters related to external synchronization Parameter Description INTEXT CAT7_Byte1_bit0 HVPLL CAT7_Byte1_bit1 1 h V PLL EXSTAT signal equivalent SYNCEX CAT7_Byte1_bit2 VRSTON CAT7_Byte1_bit3 HRSTON CAT7_Byte1_bit4 BCMPON CAT7_Byte1_bit7 SSEPEXT CAT7_Byte11_bit1 These parameters should not be ar...

Page 198: ...X tal oscillation is used to generate the encoding clock ECK Fig 12 2 1 shows the system block diagram Table 12 2 10 presents the external input signals Fig 12 2 1 Internal mode 1 clock digital encoding Table 12 2 10 External input signals 1 clock digital encoding Pin Name Pin No Input Signal S0 44pin EXVIDEOY 57pin EXVIDEO 58pin Connected to 3 3V In INT mode S0 pin 44 is not controlled by SGMODE ...

Page 199: ...e 12 2 11 presents the external input signals Fig 12 2 2 Internal mode 2 clock MCK PLL Table 12 2 11 External input signal 2 clock MCK PLL Pin Name Pin No Input Signal S0 44pin EXVIDEOY 57pin EXVIDEO 58pin Connected to 3 3V In INT mode S0 pin 44 is not controlled by SGMODE so any I O setting can be set However under the CXD3172AR default values S0 is set to input Therefore to set input pull it up ...

Page 200: ...ssive filtering in accordance with the external LPF specifications However active filtering is recommended since it provides higher performance Fig 12 2 3 shows the PCOMP output waveform when a lock is applied Fig 12 2 4 shows the PCOMP output waveform without a lock From measurements using our evaluation board Apply a trigger to the ECK DHD signal output from S2 pin 47 and view the PCOMP output w...

Page 201: ...quency NTSC 60Hz PAL 50Hz System configuration The line lock mode master signal is the power supply square wave A power supply square wave 3 3V amplitude digital signal obtained by waveform rectifying the AC power supply is input to S0 pin 44 In addition in line lock mode a 27 000MHz clock is used as the input to ECK pin 88 The MODESEL operation mode setting settings in this case are shown in Tabl...

Page 202: ...lock mode Table 12 2 14 External input signals Line lock mode Pin Name Pin No Input Signal S0 44pin 3 3V oscillating digital signal EXVIDEOY 57pin EXVIDEO 58pin Connected to 3 3V CXD3172AR 42 43 88 87 86 X tal 27 000MHz 46 47 48 44 49 57 58 ESCI ESCO ECK PCOMP EXVIDEOY EXVIDEO S0 S1 S4 S3 S2 MCK 3 3V LPF V PLL VCO LC WAVE FORMER ACIN ACIN 3 3 V amplitude digital signal ...

Page 203: ...e filter in accordance with the external LPF specifications However active filter is recommended since it provides higher performance Fig 12 2 6 shows the PCOMP output waveform when a lock is applied Fig 12 2 7 shows the PCOMP output waveform without a lock From measurements using our evaluation board Apply a trigger to the external power supply square wave S0 pin 44 input and view the PCOMP outpu...

Page 204: ...n board layout as well as the electrical characteristics and temperature characteristics of the components used If you want to use these circuits in your own set please be sure to check PLL stability jitter supply voltage fluctuations and temperature fluctuations Fig 12 2 8 WAVE FORMER Fig 12 2 9 LPF Ｖ PLL Fig 12 2 10 VCO using 760H CCD LC oscillation is typically used in the MCK VCO circuit with ...

Page 205: ...vide the block diagram of this system by Ver1 2 0 ECK 28MHz INT ECK 27MHz LL switching system set automatically external circuit required This system uses an external circuit to automatically detect whether there is an external VD input and automatically switches between LL and INT ECK input must be switched in each mode INT LL We provide the block diagram of this system by Ver1 2 0 Table 12 2 15 ...

Page 206: ...ts an explanation of the parameters based on the numbers in the flow chart Fig 12 2 11 System Switching Control Flow 1 SYSSELON SYSSELON is a parameter for turning system switching control ON OFF Table 12 2 16 SYSSELON Parameter Parameter Description SYSSELON CAT12_Byte13_bit1 0 h System configuration switching function OFF 1 h System configuration switching function ON 2 When SYSSELON is set to O...

Page 207: ...when SYSSELON 1 h SGMODE0 CAT12_Byte18_bit0 7 SGMODE when SYSSELFLG 0 h valid only when SYSSELON 1 h SGMODE1 CAT12_Byte19_bit0 7 SGMODE when SYSSELFLG 1 h valid only when SYSSELON 1 h When using this function do not assign SGMODE to a port Also do not change the SGMODE setting through serial communication Example system switching control parameter settings for 760H NTSC In this example the ECK 28M...

Page 208: ...ers based on the numbers in the flow chart Fig 12 2 12 YDLY switching control flow 1 YDLYOFF YDLYOFF is a parameter for turning YDLY switching control ON OFF Table 12 2 20 YDLYOFF Parameter Parameter Description YDLYOFF CAT12_Byte13_bit0 0 h YDLY switching function ON 1 h YDLY switching function OFF 2 When YDLYOFF is set to OFF YDLYOFF 1 h the YDLY value does not change The value originally set fo...

Page 209: ...d only when YDLYOFF 0 h YDLY1 CAT12_Byte15_bit0 3 YDLY value when YDACCKSEL 1 h valid only when YDLYOFF 0 h Example YDLY switching control parameter settings for 760H NTSC system configured using Sony evaluation board The following procedure is used for YDLY switching assumes DACMODE 1 h using the ECK 28MHz MODESEL 6 h and ECK 27MHz MODESEL 8 h systems respectively on the Sony evaluation board 1 S...

Page 210: ...there is not external VD input to S0 pin 44 the internal system is automatically switched to INT mode VCO is switched to X tal oscillation by the HVPLL signal output from Pn1 in the diagram Note When the VCO is switched please terminate VCO oscillation on the unused side in order to prevent noise For details see the applied schematic titled Circuit Figure of Internal Line Lock Fig 12 2 13 ECK 27MH...

Page 211: ...ch is set to the High position the following operations are performed SYSSELFLG which is assigned to a specified port is set to 1 h to switch MODESEL SGMODE to the LL setting The MCK switching circuit is switched to the VCO position MCK clock supply The ECK switching circuit is switched to the 27MHz position ECK 27MHz clock supply When switching from LL to INT when the DIP switch is set to the Low...

Page 212: ...ng circuit is switched to the VCO position MCK clock supply The ECK switching circuit is switched to the 27MHz position ECK 27MHz clock supply When switching from LL to INT when there is no more external VD input the following operations are performed SYSSELFLG which is assigned to a specified port is set to 0 h to switch MODESEL SGMODE to the INT setting The MCK switching circuit is switched to t...

Page 213: ...med If Ext VD presence is detected RESET output is switched from High to Low and the CXD3172AR is reset In addition for the period where RESET output Low INT LL Change signal output is switched from Low to High The INTSW input at this time is always High Fig 12 2 17 Timing for switch from INT to LL based on external VD input INTSW input High EXT VD input INT LL Change signal output XRST VD Detecti...

Page 214: ...rnal VD input INTSW input Low High While INTSW Low INT LL Change signal output is output at Low regardless of whether Ext VD is present or absent After INTSW input switches from Low to High Ext VD presence absence detection begins If Ext VD presence is detected then RESET output is switched from High to Low and the CXD3172AR is reset In addition for the period where RESET output Low INT LL Change ...

Page 215: ... signal output Low is maintained regardless of whether Ext VD is present or absent Fig 12 2 20 Timing for switch from LL to INT based on INTSW input 5 RESET output timing when there is an external RESET signal When a RESET signal is received from the exterior the CXD3172AR is force reset so RESET output is output It does not matter whether or not the external VD detection circuit itself is reset F...

Page 216: ...pared against the MCK frequency divided HD MCK HD signal inside the CXD3172AR In addition in VS Lock Mode VSL the 27 000MHz clock is used for input to ECK pin 88 In this case the MODESEL operation mode setting is as shown in Table 12 2 13 We recommend using X tal oscillation for the VCXO on the MCK side A system block diagram is shown in Fig 12 2 22 The external input signal is presented in Table ...

Page 217: ...the specifications of the external LPF Note that we recommend an active filter since active filters have better performance Fig 12 2 23 shows the PCOMP output waveform when the lock is on Fig 12 2 24 shows the PCOMP output waveform when the lock is off These waveforms are the results of measurements made using our evaluation board Apply a trigger to the external video signal and look at the PCOMP ...

Page 218: ...circuit 12 2 7 Using the Internal SYNCSEP Internal SYNCSEP divides the SYNC of the external video luminance signal signal which has passed through LPF input to EXVIDEOY pin 57 between VD and HD when using VS lock or VBS lock The internal SYNCSEP power pins are AVD5 pin 56 and AVS5 pin 59 DC bias is supplied from EXVIDEO pin 58 to EXVIDEOY pin 57 In VBS Lock Mode EXVIDEO pin 58 also serves as exter...

Page 219: ... divided HD MCK HD signal are phase compared inside the CXD3172AR In addition the 27 000MHz clock is used for input to ECK pin 88 In this case the MODESEL operation mode setting is as shown in Table 12 2 13 We recommend using X tal oscillation for the VCXO on the MCK side A system block diagram is shown in Fig 12 2 26 The external input signal is presented in Table 12 2 25 Fig 12 2 26 VS VSL S mod...

Page 220: ...ch the specifications of the external LPF Note that we recommend an active filter since active filters have better performance Fig 12 2 27 shows the PCOMP output waveform when the lock is on Fig 12 2 28 shows the PCOMP output waveform when the lock is off These waveforms are the results of measurements made using our evaluation board Apply a trigger to EXT HD and look at the PCOMP output waveform ...

Page 221: ...CXD3172AR s internal vertical direction counter The EXT HD signal and MCK frequency divided HD MCK HD signal are phase compared inside the CXD3172AR In addition the 27 000MHz clock is used for input to ECK pin 88 In this case the MODESEL operation mode setting is as shown in Table 12 2 13 We recommend using X tal oscillation for the VCXO on the MCK side A system block diagram is shown in Fig 12 2 ...

Page 222: ... we recommend an active filter since active filters have better performance Fig 12 2 30 shows the PCOMP output waveform when the lock is on Fig 12 2 31 shows the PCOMP output waveform when the lock is off These waveforms are the results of measurements made using our evaluation board Apply a trigger to D SYNC and look at the PCOMP output waveform to check whether the lock is on Fig 12 2 30 PCOMP o...

Page 223: ...EO Y input to EXVIDEOY pin 57 is divided inside the CXD3172AR between a vertical direction signal EXT VD and horizontal direction signal EXT HD EXT VD resets the CXD3172AR s internal vertical direction counter The EXT HD signal and MCK frequency divided HD MCK HD signal are phase compared inside the CXD3172AR The burst component extracted inside the CXD3172AR from EXT VIDEO input to EXVIDEO pin 58...

Page 224: ... 57 are phase compared and the result of the comparison is output through PCOMP pin 42 The PCOMP signal is applied to the LPF H PLL and fed back to the VCXO circuit on the MCK side to form the horizontal direction PLL The polarity of the PCOMP signal may be switched using PCMPINV CAT7_Byte2_bit4 An active or passive filter can be selected to match the specifications of the external LPF Note that w...

Page 225: ...plified and digitized and the resulting signal is phase compared against the FSC signal The result of this phase comparison is output through S2 pin 47 as the FSC comparison output The FSC comparison output should be applied to an LPF SC and fed back to the VCXO on the 8FSC side to form the subcarrier PLL PCOMP output Ch1 Ch2 TRIGGER PCOMP Waveforms Instability 20 0us DIV EXT VIDEO EXVIDEOY input ...

Page 226: ...deo luminance signal EXT VIDEO Y input to EXVIDEOY pin 57 is divided inside the CXD3172AR between a vertical direction signal EXT VD and horizontal direction signal EXT HD EXT VD resets the CXD3172AR s internal vertical direction counter The EXT HD signal resets the CXD3172AR s internal horizontal direction counter The burst component extracted inside the CXD3172AR from EXT VIDEO input to EXVIDEO ...

Page 227: ... against noise in cases where no external video signal is input The phase of the FSC signal output from S4 pin 49 must be adjusted and the signal must be re input to S3 pin 48 Internal phase comparison FSC phase comparison The burst component of EXT VIDEO which is input to EXTVIDEO pin 58 from SYNCSEP inside the CXD3172AR is amplified and digitized and the resulting signal is phase compared agains...

Page 228: ...counter inside the CXD3172AR EXT CLK which is synchronized to the external reset signal must be input to ECK pin 88 or MCK pin 43 Note that the configuration in this case is different from that of the 1 clock digital encoder system or 2 clock MCK PLL system A block diagram of the 1 clock digital encoder system is shown in Fig 12 2 36 A block diagram of the 2 clock MCK PLL system is shown in Fig 12...

Page 229: ...ted 3 3V power supply The EXT LALT is used with PAL so S3 pin 48 may be left OPEN or set as desired in NTSC systems Table 12 2 30 Related parameters Parameter Description DZHWID CAT7_Byte6_bit0 3 Horizontal direction reset dead band width adjustment 0 15 Pixel DZVWID CAT7_Byte6_bit4 7 Vertical direction reset dead band width adjustment 0 15 H PALSEQ CAT1_Byte7_bit3 Change LALT control field for PA...

Page 230: ... to prevent short circuiting during initialization insert a resistor with approximately 10k ohm resistance Fig 12 2 38 Measure to prevent shorting of CXD3172AR I O pins If the pins are not being used as input pins e g in INT mode then they can be left open under the output mode setting Table 12 2 31 CXD3172AR I O pins and input mode settings Setting Parameters Pin Name Pin No CAT1_Byte7 8 Initial ...

Page 231: ...ys in the various external synchronization modes Values which are adjusted through key operations are saved to the parameters in Table 12 2 34 Saved values written to EEPROM when a key is released are applied to SFTV SFTH during initialization and when the external synchronization mode is switched Table 12 2 33 Parameters Controlled by Keys in Each External Synchronization Mode External Synchroniz...

Page 232: ...BSLHR 4 h SFTVL M VRHR 5 h SFTVL M SFTHL M VSL S A h SFTVL M VSL D F h SFTVL M Table 12 2 36 SFTV and SFTH Adjustment Parameters Which are Not Key Controlled Parameter Description FIXPHL CAT17_Byte9_bit0 7 Parameter for setting SFTH not Controlled by Keys LSB FIXPHM CAT17_Byte10_bit0 1 Parameter for setting SFTH not Controlled by Keys MSB FIXPVL CAT17_Byte11_bit0 7 Parameter for setting SFTV not C...

Page 233: ...color temperature 0 1 0 2 Push SG Shifter 0 1 1 6 Hold SG Shifter 1 0 0 1 User fixed value 1 SG Shifter 1 0 1 5 user fixed value 2 SG Shifter 1 1 0 3 user fixed value 3 SG Shifter 1 1 1 7 user fixed value 4 SG Shifter 12 3 2 Key Operations Key operation procedures Manual WB gain adjustment for the WB function and external synchronization phase adjustment both use the following parameters as keys S...

Page 234: ...AT17_Byte20_bit0 1 Sets the key processing count for the initial period Common KEYRPFLD CAT17_Byte21_bit0 7 Sets the key processing interval for the continuous period Only valid for WB processing SFTSTEP CAT17_Byte22_bit0 4 Shifter operation speed setting STEP width Common Fig 12 3 1 SFTUP SFTDWN key arrangement Fig 12 3 2 SFTUP SFTDWN key assignments SFTUP and SFTDWN are assigned to ports Pn1 and...

Page 235: ...ction phase adjustment value MSB Table 12 3 5 Parameters for saving SFTV SFTH adjustment values Parameter Description CTRLSFTHL CAT17_Byte1_bit0 7 Parameter for saving SFTH adjustment value at key release LSB CTRLSFTHM CAT17_Byte2_bit0 1 Parameter for saving SFTH adjustment value at key release MSB CTRLSFTVL CAT17_Byte3_bit0 7 Parameter for saving SFTV adjustment value at key release LSB CTRLSFTVM...

Page 236: ...scription WBR CAT4_Byte1 White balance gain R WBB CAT4_Byte3 White balance gain B Table 12 3 8 Parameter for saving WBR WBB adjustment value Parameter Description PLRGAIN CAT15_Byte33 Push lock R gain Parameter for saving WBR adjustment value when key is released PLBGAIN CAT15_Byte34 Push lock B gain Parameter for saving WBB adjustment value when key is released WB gain parameters when using prese...

Page 237: ... External Microcomputer DSP EEPROM Interface Connection Method The wiring for each pin is given in the table below Table 12 4 1 CXD3172AR Wiring with a Microcomputer Pin name Pin Number Description SIFSEL 13 Low XCS 15 Chip selection input SI 16 Serial settings input SO 17 Serial data output SCK 18 Serial clock input VD Auxiliary signal for communication timing control Output from S3 Pin 48 S3SEL ...

Page 238: ...nication Timing The CXD3172AR loads data in 8 bit units at the rising edge of SCK when XCS is low The serial output is sent at the falling edge of SCK in synchronization with the serial input You must leave at least SCK 1 clock division between byte data The communication data is LSB first Additionally make SCK H or pull up before making XCS low For details on data strings see the following sectio...

Page 239: ... 07h 00h 01h 02h Dummy packets for receipt only 00h Sends as many 00h as the number of bytes received Explanation of Command Transmission Specification Data of first byte Total number of valid bytes in a packet if 00h judged a dummy Data of second byte Command code CAT Write read category number STBN Write read start byte number BYTEn Number of bytes to write read if CAT is specified only in the s...

Page 240: ...h Specify and read actual EEPROM address BYTEn 1 Read data the specified amount Specify and write actual EEPROM address 02h 01h Write all to EEPROM 02h 01h Explanation of Command Reception Specification Data of first byte Total number of valid bytes in a packet otherwise an error code Fnh Data of second byte Dummy 01h read data or echo back write data BYTEn Number of bytes to write read Error code...

Page 241: ...ohibited Period Other Than for EEPROM Write and Table 12 4 5 Communication Prohibited Period of EEPROM Write Fig 12 4 3 Microcomputer Communication Format Fig 12 4 4 DSP Response Timing After the DSP receives a packet it responds when it receives the next Flexible max 32 Bytes SCK XCS SI COMmand SO Start Word Hi Z Hi Z STatus word Byte1 Byte2 Byte3 Byte32 Start Word Byte4 Byte30 Byte31 Byte1 Byte2...

Page 242: ...prohibited period Serial Communication Prohibited Period Power on DSP initialization Fig 12 4 6 Communication Prohibited Period during CXD3172AR Initialization Serial communication cannot be received in the initial period from reset to 10 fields Monitor the VD pulse for example and wait until the initial period is over XCS Command latch Commands reflect on parameters at the next VD latch Command l...

Page 243: ...ble 12 4 4 Communication Prohibited Period Other Than for EEPROM Write Command prohibit_period_2 prohibit_period_3 Register READ Register WRITE 500 us EEPROM category READ Specify and Read EEPROM direct address 3 0 ms If it depends on the VD falling edge communication is also prohibited for 2HD To allow for firmware processing for each field ensure a prohibit_period_3 including a 2HD period after ...

Page 244: ...it_period_4 Specify and Write EEPROM direct address Specify and Write EEPROM category 18 field Write all EEPROM categories 360 field When not using communication with the External Microcomputer If RS 232C communication is used set SIFSEL to high and follow the RS 232C communication settings Also set XCS and SCK to high if there is no communication with an external microcomputer or via serial inter...

Page 245: ...yte35_bit0 7 80 h GMATCB CAT2_Byte36_bit0 7 80 h RYGAIN1 CAT2_Byte37_bit0 7 26 h BYGAIN1 CAT2_Byte38_bit0 7 1B h RYHUE1 CAT2_Byte39_bit0 7 D5 h BYHUE1 CAT2_Byte40_bit0 7 E9 h BLACKS1 CAT2_Byte55_bit0 7 00 h BLACKS2 CAT2_Byte56_bit0 7 00 h WBR CAT4_Byte1_bit0 7 40 h WBG CAT4_Byte2_bit0 7 40 h WBB CAT4_Byte3_bit0 7 20 h PG display ON OFF The following parameter is used to turn the PG display ON OFF ...

Page 246: ...formation on how to make this setting Fig 12 5 1 Pattern types Pattern settings Note that the images shown above are for reference purposes only The patterns that are actually output by the PG will differ slightly from them Table 12 5 5 Raster color settings Parameter Setting Value Description 0 h Sets raster color to W 1 h Sets raster color to Ye 2 h Sets raster color to Cy 3 h Sets raster color ...

Page 247: ...9_Byte37_bit3 1 h Adds a ramp to and displays the PG selected by PGPAT if impulse is set then the display is reversed Fig 12 5 2 Pattern types with ramp added Note that the images shown above are for reference purposes only The patterns that are actually output by the PG will differ slightly from them It is not possible to add a ramp under serial settings Horizontal color bar Vertical ramp Raster ...

Page 248: ...s H Vsettings Note that the images shown above are for reference purposes only The patterns that are actually output by the PG will differ slightly from them The PG and ramp are linked together so if the PG is changed between horizontal and vertical the ramp will also change between vertical and horizontal Therefore it is not possible to display combinations in which a horizontal ramp is added to ...

Page 249: ...hese settings Table 12 5 10 shows color reproduction settings which are nearly ideal Table 12 5 9 Parameters for setting CR and CB line information Parameter Setting Value Description PGSDCRS2 CAT9_Byte39_bit0 7 00 h FF h CR_S2 serial setting Ye Mg PGSDCRS1 CAT9_Byte40_bit0 7 00 h FF h CR_S1 serial setting Cy G PGSDCBS2 CAT9_Byte41_bit0 7 00 h FF h CB_S2 serial setting Ye G PGSDCBS1 CAT9_Byte42_bi...

Page 250: ...rite CAT1 into EEPROM 4 Set SSELOFF to 0 back Table 12 6 1 S0IN S0IN S0 pin INput Parameter category CAT1_Byte7_bit6 Outline Selects the S0 pin input output signal Setting range 0 h 1 h Initial value 1 h VRI INPUT Description 0 h DHD OUTPUT 1 h VRI INPUT Note F W controls this pin during the external synchronization Refer to 12 2 Using external synchronization for details Table 12 6 2 S1IN S1IN S1...

Page 251: ... h 7 h Initial value 0 h DHD OUTPUT Description Each signal is output according to the following settings 0 h DHD 1 h DVD 2 h HD 3 h VD 4 h NRYBY 5 h Digital YOUT 7 6 h FLD 7 h Analog shift FSC input Note F W controls this pin during the external synchronization VBS Lock Table 12 6 5 S4SEL S4SEL S4 pin SELect Parameter category CAT1_Byte8_bit6 7 2bit Outline Selects the S4 pin output signal Settin...

Page 252: ... CAT22 SOUT1 through serial communication Settings Marker position indicators during camera adjustment signal output are set by setting numerical values for MSK0HSET and MSK0VSET When these are set the indicators are mixed with the Y signal and makers are displayed on the screen These set values are the same as the position indicated by the mask 0 starting point address The marker display can be t...

Page 253: ... Description AJSTOUTL M CAT22_Byte2_bit0 7 CAT22_Byte3_bit0 1 AD sampling data output YOUTL M CAT22_Byte54_bit0 7 CAT22_Byte57_bit0 Y sampling data output RYOUTL M CAT22_Byte55_bit0 7 CAT22_Byte57_bit1 R Y sampling data output BYOUTL M CAT22_Byte56_bit0 7 CAT22_Byte57_bit2 B Y sampling data output ...

Page 254: ...LHR 5 h VRHR A h VSL S F h VSL D No noise effects Noise appears in AGC area Severe noise effects Outside specified range For details on MODESEL settings see 6 CCD Type Selection For information on noise countermeasures see 3 6 Noise Countermeasures in the application 13 2 Operation Mode Control during Digital Output Only a limited number of operation mode MODESEL and external synchronization mode ...

Page 255: ... are controlled by SGMODE Please do not change parameters controlled by FW CAT2 PICT1 Byte bit Parameter FW control timing Control methods Except CPUHOLD 1 Byte4_bit2 5 VHAPG VHAPGCTL CAT12_Byte8_bit0 1 h Byte6_bit7 YGAMSON Byte7_bit0 YGAMSLV Byte7_bit1 YGAMSMTH Byte7_bit2 4 YGAMSEL Byte7_bit5 7 YKNEESEL GAMCTL CAT12_Byte9_bit0 1 h Byte8 YGAIN YGAINCTL CAT12_Byte8_bit3 1 h Byte10_bit0 5 SETUP SETU...

Page 256: ... CAT12_Byte5_bit1 1 h Byte2 WBG Reset AWBHOLD CAT12_Byte5_bit1 1 h or Set the GGAIN CAT15_Byte4 Byte3 WBB Byte6 WBYUP Byte7 WBYDWN Every field AWBHOLD CAT12_Byte5_bit1 1 h CAT5 OPDWND1 Byte bit Parameter FW control timing Control methods CPUHOLD 1 以外 Byte1 8 Fix Every field Please do not change parameters controlled by FW CAT6 TG Byte bit Parameter FW control timing Control methods Except CPUHOLD ...

Page 257: ...d by FW CAT8 FEADJ EVRI Byte bit Parameter FW control timing Control methods Except CPUHOLD 1 Byte3 AGCCNT AEHOLD CAT12_Byte5_bit2 1 h Byte4 IRISVCNT Every field If you set AEHOLD CAT12_Byte5_bit2 to 1 h and MIRIS CAT14_Byte1_bit1 to 0 h the setting value can be changed CAT10 DIF Byte bit Parameter FW control timing Control methods Except CPUHOLD 1 Byte1_bit1 DIF27 Reset These parameters are contr...

Page 258: ...tion or otherwise under any patents or other rights Application circuits shown if any are typical examples illustrating the operation of the devices Sony cannot assume responsibility for any problems arising out of the use of these circuits SS HQ1 Application Notes Not for sale Jan 2005 Ver 1 0 0 Editor and Publisher Sony Corporation Semiconductor Solutions Network Company C 2005 Sony Corporation ...

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