Sony IPELA SNC-RZ30N, Service Manual

Page: 78 / 128

5-4
SNC-RZ30N/RZ30P (E)
HD6417615ARF (HITACHI)
157
160
165
170
175
180
185
190
195
200
205
208
32-BIT RISC CPU
—TOP VIEW—
104
100
95
90
85
80
75
70
65
60
55
53
156 155 150 145 140 135 130 125 120 115 110 105
1 5
10 15 20 25 30 35 40 45 50 52
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
IRL3
IRL2
IRL1
IRL0
NMI
ASEMODE
GND
RES
GND
CAP2
CAP1
V
CC
MD4
MD3
MD2
MD1
MD0
V
CC
EXTAL
GND
XTAL
V
CC
CKIO
CKPREQ
/CKM
CKPACK
GND
IVECF
TDO
TDI
TCK
TMS
TRST
V
CC
D0
GND
D1
D2
D3
D4
D5
D6
V
CC
D7
D8
GND
D9
D10
D11
D12
V
CC
D13
GND
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
D14
D15
D16
D17
D18
V
CC
D19
GND
GND
D20
D21
D22
D23
V
CC
V
CC
D24
GND
D25
D26
D27
D28
D29
D30
V
CC
D31
GND
GND
A0
V
CC
A1
A2
A3
A4
A5
A6
A7
V
CC
A8
GND
A9
A10
A11
A12
A13
A14
A15
V
CC
A16
GND
A17
A18
A19
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
O
O
O
O
—
—
O
—
—
—
I
—
O
O
O
O
O
O
O
O
O
O
O
O
O
—
O
—
O
O
O
O
O
O
I
O
I
I
O
O
O
—
—
O
—
—
I/O
I/O
I/O
I/O
—
I/O
A20
A21
A22
A23
V
CC
V
CC
A24
GND
GND
GND
WAIT
V
CC
RAS
CAS
/
OE
DQMUU/
WE3
DQMUL/
WE2
DQMLU/
WE1
DQMLL/
WE0
CAS3
CAS2
CAS1
CAS0
CKE
RD
REFOUT
GND
BS
V
CC
RD/
WR
CS0
CS1
CS2
CS3
CS4
BUSHIZ
BH
DREQ1
DREQ0
DACK1
DACK0
BRLS
V
CC
V
CC
BGR
GND
GND
PB15/SCK1
PB14/RXD1
PB13/TXD1
PB12/SRCK2/
RTS
/STATS1
V
CC
PB11/SRS2/
CTS
/STATS0
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
—
I
—
I/O
O
I
I/O
I/O
I
I
I
I
—
I
—
I
I
I
I
I/O
O
—
I
—
O
O
O
O
O
O
GND
PB10/SRXD2/TIOCA1
PB9/STCK2/TIOCB1/TCLKC
PB8/STS2/TIOCA2
PB7/STXD2/TIOCB2/TCLKD
PB6/SRCK1/SCK2
PB5/SRS1/RXD2
PB4/SRXD1/TXD2
PB3/STCK1/TIOCA0
PB2/STS1/TIOCB0
V
CC
PB1/STXD1/TIOCC0/TCLKA
GND
PB0/TIOCD0/TCLKB/WOL
PA13/SRCK0
PA12/SRS0
PA11/SRXD0
PA10/STCK0
PA9/STS0
PA8/STXD0
WDTOVF
/PA7
PA6/FTCI
V
CC
PA5/FTI
GND
PA4/FTOA
CKPO/FTOB
PA2/LNKSTA
PA1/EXOUT
PA0/EXPOSE
RXER
RXDV
COL
CRS
GND
RXCLK
V
CC
ERXD0
ERXD1
ERXD2
ERXD3
MDIO
MDC
V
CC
TXCLK
GND
TXEN
ETXD0
ETXD1
ETXD2
ETXD3
TXER
I
I
I
I
I
I
—
I
—
I
I
—
I
I
I
I
I
—
I
—
O
—
I/O
I
O
—
O
O
I
I
I
I
—
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
—
I/O
I/O
I/O
I/O
—
I/O
—
I/O
I/O
I/O
I/O
I/O
—
I/O
—
—
I/O
I/O
I/O
I/O
—
—
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
—
—
O
—
O
O
O
O
O
O
O
—
O
—
O
O
O
O
O
O
O
—
O
—
O
O
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
INPUTS
ASEMODE
BRLS
BUSHIZ
CKPREQ
/CKM
COL
CRS
CTS
DREQ0, DAEQ1
ERXD0 - ERXD3
EXTAL
FTCI
FTI
IRL0
-
IRL3
LNKSTA
MD0 - MD4
NMI
PLLCAP1, PLLCAM2
RES
RXCLK
RXD1, RXD2
RXDV
RXER
SRCK0 - SRCK2
SRS0 - SRS2
SRXD0 - SRXD2
STCK0 - STCK2
TCK
TCLKA, TCLKB,
TCLKC, TCLKD
TDI
TMS
TRST
TXCLK
WAIT
: ASE MODE INPUT
: BUS RELEASE
: BUS HIGH IMPEDANCE
: CLOCK PAUSE REQUEST
: COLLISION
: CARRIER SENSE
: TRANSMIT PERMISSION
: DMAC REQUEST
: RECEIVE DATA
: CRYSTAL OSCILLATOR TERMINAL
: COUNTER CLOCK
: INPUT CAPTURE
: INTERRUPT REQUEST
: LINK STATUS
: MODE SET
: NONMASKABLE INTERRUPT
: PLL CAPACITANCE CONNECTION
: RESET
: RECEIVE CLOCK
: RECEIVE DATA
: RECEIVE DATA ENABLE
: RECEIVE ERROR
: SERIAL RECEIVE CLOCK
: SERIAL RECEIVE SYNCHRONIZATION
: SERIAL RECEIVE DATA
: SERIAL TRANSMIT CLOCK
: TEST CLOCK
: TPU TIMER CLOCK
: TEST DATA INPUT
: TEST MODE SELECT
: TEST RESET
: TRANSMIT CLOCK
: WAIT
OUTPUTS
A0 - A24
BGR
BH
BS
CAS
CAS0
-
CAS3
CKE
CKPACK
CKPO
CS0
-
CS4
DACK0, DACK1
DQMLL/
WE0
DQMLU/
WE1
DQMUL/
WE2
DQMUU/
WE3
ETXD0 - ETXD3
EXOUT
FTOA, FTOB
IVECF
MDC
OE
RAS
RD
RD/
WR
REF OUT
RTS
STATS0, STATS1
STXD0 - STXD2
TDO
TXD1, TXD2
TXEN
TXER
WDTOVF
WOL
XTAL
INPUTS/OUTPUTS
CKIO
D0 - D31
MDIO
PA0 - PA13
PB0 - PB15
SCK1, SCK2
STS0 - STS2
TIOCA0 - TIOCA2,
TIOCB0 - TIOCB2,
TIOCC0, TIOCD0
: ADDRESS BUS
: BUS GRANT
: BURST HINT
: PASS CYCLE START
: COLUMN ADDRESS STROBE FOR SDRAM
: COLUMN ADDRESS STROBE FOR DRAM
: CLOCK ENABLE
: CLOCK PAUSE ACKNOWLEDGE
: CLOCK
: CHIP SELECT
: DMAC ACKNOWLEDGE
: LSB BYTE ACCESS
: THIRD BYTE ACCESS
: SECOND BYTE ACCESS
: MSB BYTE ACCESS
: TRANSMIT DATA
: GENERAL PURPOSE EXTERNAL OUTPUT
: OUTPUT COMPARE
: INTERRUPT VECTOR FETCH CYCLE
: MANAGEMENT DATA CLOCK
: OUTPUT ENABLE
: LOW ADDRESS STROBE
: READ
: READ/WRITE
: REFRESH OUT
: TRANSMIT REQUEST
: STATUS (CPU, DMAC, E-DMAC)
: SERIAL TRANSMIT DATA
: TEST DATA OUTPUT
: TRANSMIT DATA
: TRANSMIT ENABLE
: TRANSMIT ERROR
: WATCH DOG TIMER OVERFLOW
: WAKE ON LAN
: CRYSTAL OSCILLATOR TERMINAL
: SYSTEM CLOCK
: DATA BUS
: MANAGEMENT DATA I/O
: GENERAL PORT
: GENERAL PORT
: SERIAL CLOCK
: SERIAL TRANSMIT SYNCHRONIZATION
: TPU INPUT CAPTURE/OUTPUT COMPARE
IC