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BD (MD) BOARD IC316 M30610MCA-272FP (MD MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1
JOG0
I
Rotary encoder jog dial pulse input terminal Not used (fixed at “H”)
2
JOG1
I
Rotary encoder jog dial pulse input terminal Not used (fixed at “H”)
3
DAOUT0
O
Monitor output terminal for the test C1 error rate is output when test mode
4
DAOUT1
O
Monitor output terminal for the test ADER is output when test mode
5
SQSY
I
Subcode Q sync (SCOR) input from the CXD2652AR (IC121)
“L” is input every 13.3 msec Almost all, “H” is input
6
REMCON
I
Remote control signal input terminal Not used (fixed at “H”)
7
EMP
O
Emphasis control signal output to the A/D, D/A converter (IC201)
8
BYTE
I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
9
CNVSS
—
Ground terminal
10
XT-IN
I
Sub system clock input terminal Not used (fixed at “L”)
11
XT-OUT
O
Sub system clock output terminal Not used (pull down)
12
SYSTEM-RST
I
System reset signal input from the reset signal generator (IC706) and master controller (IC707)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (7 MHz)
14
GND
—
Ground terminal
15
XIN
I
Main system clock input terminal (7 MHz)
16
+3.3V
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal (fixed at “H” in this set)
18
AMUTE
O
Audio line muting on/off control signal output terminal “L”: line muting on
Not used (pull down)
19
PWR-DWN
I
Power down detection signal input terminal “L”: power down, normally: “H”
20
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2652AR (IC121)
“L” is input every 13.3 msec Almost all, “H” is input
21
STB
O
Strobe signal output to the power supply circuit “H”: power on, “L”: standby mode
Not used (pull down)
22
DARST
O
Reset signal output terminal “L”: reset Not used (pull down)
23
XINT
I
Interrupt status input from the CXD2652AR (IC121)
24
DA-EN
O
Enable signal output to the A/D, D/A converter (IC201) (for D/A converter block)
“L”: enable
25
AD-EN
O
Enable signal output to the A/D, D/A converter (IC201) (for A/D converter block)
“L”: enable
26
MEC-BUSY
O
MD mechanism controller busy status monitor output to the master controller (IC707)
27
FLCS
O
Chip select signal output terminal Not used (pull down)
28
FLCLK
O
Display serial data transfer clock signal output terminal Not used (pull down)
29
—
I
Not used (fixed at “L”)
30
FLDATA
O
Display serial data output terminal Not used (pull down)
31
TXD
O
UART communication data output to the master controller (IC707)
32
RXD
I
UART communication data input from the master controller (IC707)
33
CLK
I
Serial clock signal input from the master controller (IC707)
34
MAS-BUSY
I
Master controller busy status monitor input from the master controller (IC707)
35
SWDT
O
Writing data output to the CXD2652AR (IC121)
36
SRDT
I
Reading data input from the CXD2652AR (IC121)
37
SCLK
O
Serial clock signal output to the CXD2652AR (IC121)
38
XLAT
O
Serial data latch pulse signal output to the CXD2652AR (IC121)
39
—
I
Not used (fixed at “L”)
40
DIG-RST
O
Reset signal output to the CXD2652AR (IC121) and BH6511FS (IC152) “L”: reset
Summary of Contents for HCD-MD1EX - System
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