HAP-Z1ES
91
Pin No.
Pin Name
I/O
Description
78, 79
VDD_INT
-
Power supply terminal (+1.1V) (for core)
80 to 82
FLAG1 to FLAG3
O
Interrupt request signal output terminal Not used
83
MLBCLK
I
Media local bus clock signal input terminal Not used
84
MLBDAT
I/O
Media local bus data input/output terminal Not used
85
MLBDO
O
Media local bus data output terminal Not used
86
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
87
MLBSIG
I/O
Media local bus signal input/output terminal Not used
88
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
89
MVBSO
O
Media local bus signal output terminal Not used
90
!TRST!
I
Test reset signal input terminal Not used
91
!EMU!
O
Emulation status signal output terminal Not used
92
TDO
O
Test data output terminal Not used
93
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
94
VDD_INT
-
Power supply terminal (+1.1V) (for core)
95
TDI
I
Test data input terminal Not used
96
TCK
I
Test clock signal input terminal Not used
97
VDD_INT
-
Power supply terminal (+1.1V) (for core)
98
nRESET
I
Reset signal input from the FPGA “L”: reset
99
TMS
I
Test mode selection signal input terminal Not used
100
VDD_INT
-
Power supply terminal (+1.1V) (for core)
Summary of Contents for HAP-Z1ES
Page 119: ...MEMO HAP Z1ES 119 ...
