HAP-Z1ES
90
FPGA DSP BOARD IC601 ADSP-21488KSWZ-3A1 (AUDIO DSP)
Pin No.
Pin Name
I/O
Description
1
VDD_INT
-
Power supply terminal (+1.1V) (for core)
2
CLK_CFG1
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “H” in this unit
3
BOOT_CFG0
I
Boot mode selection signal input terminal Fixed at “L” in this unit
4
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
5
VDD_INT
-
Power supply terminal (+1.1V) (for core)
6
BOOT_CFG1
I
Boot mode selection signal input terminal Fixed at “L” in this unit
7
GND
-
Ground terminal
8, 9
NC
-
Not used
10
CLK_CFG0
I
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
Fixed at “L” in this unit
11
VDD_INT
-
Power supply terminal (+1.1V) (for core)
12
CLKIN
I
System clock input terminal (10 MHz)
13
XTAL
O
System clock output terminal (10 MHz)
14
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
15, 16
VDD_INT
-
Power supply terminal (+1.1V) (for core)
17
nRESETOUT/
nRESETIN
I/O
Reset signal input/output terminal Not used
18
VDD_INT
-
Power supply terminal (+1.1V) (for core)
19
DPI_P01
I
Serial data input from the FPGA
20
DPI_P02
O
Serial data output to the FPGA
21
DPI_P03
I
Serial data transfer clock signal input from the FPGA
22
VDD_INT
-
Power supply terminal (+1.1V) (for core)
23
DPI_P05
I/O
Not used
24
DPI_P04
I
Chip select signal input from the FPGA
25
DPI_P06
I/O
Not used
26
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
27, 28
DPI_P08, DPI_P07
I/O
Not used
29
VDD_INT
-
Power supply terminal (+1.1V) (for core)
30 to 36
DPI_P09 to DPI_P13,
DAI_P03, DAI_P14
I/O
Not used
37 to 39
VDD_INT
-
Power supply terminal (+1.1V) (for core)
40
DAI_P13
I
Bit clock signal input from the FPGA
41
DAI_P07
I
L/R sampling clock signal input from the FPGA
42
DAI_P19
I
Audio data input from the FPGA
43, 44
DAI_P01, DAI_P02
I/O
Not used
45
VDD_INT
-
Power supply terminal (+1.1V) (for core)
46
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
47
VDD_INT
-
Power supply terminal (+1.1V) (for core)
48
DAI_P06
I
Bit clock signal input from the FPGA
49
DAI_P05
I
L/R sampling clock signal input from the FPGA
50
DAI_P09
O
Audio data output to the FPGA
51
DAI_P10
I/O
Not used
52
VDD_INT
-
Power supply terminal (+1.1V) (for core)
53
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
54
DAI_P20
I/O
Not used
55
VDD_INT
-
Power supply terminal (+1.1V) (for core)
56 to 63
DAI_P08, DAI_P04,
DAI_P14, DAI_P18 to
DAI_P15, DAI_P12
I/O
Not used
64
VDD_INT
-
Power supply terminal (+1.1V) (for core)
65
DAI_P11
I
Interrupt request signal input from the FLAG0 (pin 77)
66, 67
VDD_INT
-
Power supply terminal (+1.1V) (for core)
68
GND
-
Ground terminal
69
THD_M
O
Thermal diode cathode output terminal Not used
70
THD_P
I
Thermal diode anode input terminal Not used
71
VDD_THD
-
Power supply terminal (for thermal diode) Not used
72 to 76
VDD_INT
-
Power supply terminal (+1.1V) (for core)
77
FLAG0
O
Interrupt request signal output to the DAI_P11 (pin 65)
Summary of Contents for HAP-Z1ES
Page 119: ...MEMO HAP Z1ES 119 ...
