HAP-Z1ES
87
Pin No.
Pin Name
I/O
Description
E1
GXB_RX1p
O
Not used
E2
GXB_RX1n
O
Not used
E3
GND_E3
-
Ground terminal
E4
VCCINT_E4
-
Power supply terminal (+1.2V)
E5
GND_E5
-
Ground terminal
E6
CLK10/DIFFCLK_4n/
REFCLK1n
I
Reset signal input from the MPU “L”: reset
E7
CLK11/DIFFCLK_4p/
REFCLK1p
I
50 MHz clock signal input terminal
E8
VCCINT_E8
-
Power supply terminal (+1.2V)
E9
GND_E9
-
Ground terminal
E10
IO/DIFFIO_R4P/
DM0R
O
Serial data transfer clock signal output to the D/A converter
E11
VCCIO6_E11
-
Power supply terminal (+3.3V)
E12
GND_E12
-
Ground terminal
E13
IO/VREFB6N0
O
Not used
F1, F2
GND_F1, GND_F2
-
Ground terminal
F3
VCCL_GXB_F3
-
Power supply terminal (+1.2V)
F4
GND_F4
-
Ground terminal
F5
VCCINT_F5
-
Power supply terminal (+1.2V)
F6
GND_F6
-
Ground terminal
F7
VCCINT_F7
-
Power supply terminal (+1.2V)
F8
GND_F8
-
Ground terminal
F9
IO_F9
O
Chip select signal output to the audio DSP
F10
IO/DIFFIO_R5P/
DQ0R
I
Serial data input from the audio DSP
F11
IO/DIFFIO_R5N/
DQ0R
O
Serial data output to the audio DSP
F12
CLK7/DIFFCLK_3P
O
Not used
F13
CLK6/DIFFCLK_3N
O
Not used
G1
GXB_TX0n
O
Receive data (negative) output to the FPGA
G2
GXB_TX0p
O
Receive data (positive) output to the FPGA
G3
VCCH_GXB
-
Power supply terminal (+2.5V)
G4
VCCINT_G4
-
Power supply terminal (+1.2V)
G5
GND_G5
-
Ground terminal
G6
VCCINT_G6
-
Power supply terminal (+1.2V)
G7
GND_G7
-
Ground terminal
G8
VCCINT_G8
-
Power supply terminal (+1.2V)
G9
IO/DIFFIO_R6P/
DQS0R/CQ0R/
DPCLK8
O
Serial data transfer clock signal output to the audio DSP
G10
IO/DIFFIO_R6N/
DEV_OE
O
Reset signal output to the audio DSP “L”: reset
G11
VCCIO6_G11
-
Power supply terminal (+3.3V)
G12
GND_G12
-
Ground terminal
G13
CLK4/DIFFCLK_2N
I
5.6448 MHz clock or 6.144 MHz clock signal input terminal
H1, H2
GND_H1, GND_H2
-
Ground terminal
H3
VCCL_GXB_H3
-
Power supply terminal (+1.2V)
H4
GND_H4
-
Ground terminal
H5
VCCINT_H5
-
Power supply terminal (+1.2V)
H6
GND_H6
-
Ground terminal
H7
VCCINT_H7
-
Power supply terminal (+1.2V)
H8
GND_H8
-
Ground terminal
H9
VCCA_H9
-
Power supply terminal (+2.5V)
H10
IO/DIQS1R/CQ0R#/
DPCLK7
O
Output enable signal output terminal for the 22.5792 MHz clock
H11
VCCIO5_H11
-
Power supply terminal (+3.3V)
H12
IO/VREFB5N0
O
Output enable signal output terminal for the 24.576 MHz clock
H13
CLK5/DIFFCLK_2P
I
Not used
J1
GXB_RX0n
I
Transmit data (negative) input from the MPU
J2
GXB_RX0P
I
Transmit data (positive) input from the MPU
Summary of Contents for HAP-Z1ES
Page 119: ...MEMO HAP Z1ES 119 ...