Sony HAP-Z1ES, Service Manual

Page: 81 / 120

HAP-Z1ES
81
Pin No. Pin Name I/O Description
T1 to T5
GPIO_2, GPIO_9,
GPIO_6, GPIO_1,
GPIO_0
- Not used
T6 KEY_COL4 - Not used
T7 KEY_ROW3 O Liquid crystal display dimmer control signal output terminal
T8 GND84 - Ground terminal
T9 VDDARM23_IN7 - Power supply terminal for the cores regulator Not used
T10 VSSSOC_CAP2 O Internal regulator output terminal (+1.1V)
T11, T12 GND79, GND80 - Ground terminal
T13, T14
VSSSOC_CAP3,
VSSSOC_CAP4
O Internal regulator output terminal (+1.1V)
T15 GND81 - Ground terminal
T16 VDDSOC_IN9 - Power supply terminal for the SOC and PU regulators (+1.42V)
T17 GND82 - Ground terminal
T18 NVCC_DRAM2 - Power supply terminal for the DDR interface (+1.5V)
T19 GND83 - Ground terminal
T20, T21
DISP0_DAT21,
DISP0_DAT16
O RGB signal (red) output to the liquid crystal display
T22 to
T25
DISP0_DAT15,
DISP0_DAT11,
DISP0_DAT12,
DISP0_DAT9
O RGB signal (green) output to the liquid crystal display
U1 LVDS0_TX0_P - Not used
U2 LVDS0_TX0_N - Not used
U3 LVDS0_TX1_P - Not used
U4 LVDS0_TX1_N - Not used
U5 KEY_COL3 O Liquid crystal display dimmer control signal output terminal
U6 KEY_ROW1 - Not used
U7 KEY_COL1 - Not used
U8 GND89 - Ground terminal
U9 VDDARM23_IN8 - Power supply terminal for the cores regulator Not used
U10 VSSSOC_CAP5 O Internal regulator output terminal (+1.1V)
U11, U12 GND85, GND86 - Ground terminal
U13, U14
VSSSOC_CAP6,
VSSSOC_CAP7
O Internal regulator output terminal (+1.1V)
U15 GND87 - Ground terminal
U16 VDDSOC_IN10 - Power supply terminal for the SOC and PU regulators (+1.42V)
U17 GND88 - Ground terminal
U18 NVCC_DRAM3 - Power supply terminal for the DDR interface (+1.5V)
U19 GND90 - Ground terminal
U20 ENET_TXD0 O Power on/off control signal output terminal for the liquid crystal display “H”: power on
U21 ENET_CRS_DV O Reset signal output to the ethernet transceiver “L”: reset
U22 to
U24
DISP0_DAT20,
DISP0_DAT19,
DISP0_DAT17
O RGB signal (red) output to the liquid crystal display
U25 DISP0_DAT14 O RGB signal (green) output to the liquid crystal display
V1 LVDS0_TX2_P - Not used
V2 LVDS0_TX2_N - Not used
V3 LVDS0_CLK_P - Not used
V4 LVDS0_CLK_N - Not used
V5, V6
KEY_ROW4,
KEY_ROW0
- Not used
V7 NVCC_LVDS2P5 - Power supply terminal for the LVDS display interface (+2.5V)
V8 GND91 - Ground terminal
V9 to
V18
NVCC_DRAM13,
NVCC_DRAM4 to
NVCC_DRAM12
- Power supply terminal for the DDR interface (+1.5V)
V19 GND92 - Ground terminal
V20 ENET_MDC O Management data clock signal output to the ethernet transceiver
V21 ENET_TX_EN - Not used
V22 ENET_REF_CLK I 25 MHz clock signal input from the ethernet transceiver
V23 ENET_MDIO I/O Two-way management data bus with the ethernet transceiver