Sony FWD-32LX1R Mounting Bracket, Service Manual

Page: 103 / 142

8-9
FWD-32LX1R
8-9
I
2
C/SMBUS
CONTROL
WRITE PULSE
READ PULSE
WRITE PULSE
READ PULSE
8-BIT
8-BIT
LP FILTER
VINT
I/O07
INT
VSS
VDD
SDA
SCL
A2
A1
A0
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
I/O00
I/O01
I/O02
I/O03
I/O04
I/O05
I/O06
I/O17
I/O10
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
INPUT
FILTER
POWER-ON
RESET
13
20
19
18
17
16
15
14
4
11
10
9
8
7
6
5
1
12
24
23
22
3
2
21
INPUT/
OUTPUT
PORTS
INPUT/
OUTPUT
PORTS
D3 (2/6) PCA9555DB-118 (IC2202)
5
V
CC
R
D
1
3 GND
CD
4 OUT
+
_
Vref
D3 (2/6) PST3629NR (IC2201)
1
CTL VCC
3
GND
4
OUT
5
C
VREF
DRIVER
TSD OCP
2
_
D3 (3/6) BA18BCOWFP-E2 (IC2406)
D3 (3/6) BA25BC0WFP-E2 (IC2405)
D3 (3/6) BA33BC0WFP-E2 (IC2404)
RY/BY
BUFFER
RY/BY
STATO
CONTROL
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR
PROGRAM VOLTAGE
GENERATOR
CHIP ENABLE
OUTPUT ENABLE
LOGIC
STB
STB
DATA LATCH
Y-DECODER
X-DECODER
ADDRESS
LATCH
CELL MATRIX
Y-GATING
LOW VCC DETECTOR
TIMER FOR
PROGRAM/ERASE
25
,
16
23
,
1
9
,
48
DQ0 TO DQ15
INPUT/OUTPUT
BUFFERS
VCC
VSS
VSS
WE
BYTE
RESET
CE
CE
A0 TO A15
A-1
37
11
47
12
26
28
24
27
46
29 - 36, 38 - 45
D3 (3/6) MBM29LV800TA-70PFTN (IC2408)
4
VCC
2 VSS
1
OUT
+
_
VREF
D3 (3/6) S-80828CNNB-B8NT2G (IC2403)
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
17
18 POLH
EXIH
POLV
EXIV
VCC
HDRV
CLAMP
VDRV
CPWID
HSCTL
C/HSYNC IN
VIDEO IN
VSEPA
VSNC IN
CVPOL
CVEXI
CPSEL
GDN
CLAMP PULSE GEN
V SYNC DET
V SYNC SEPA
SYNC SEPA
H SYNC DET
HOR. SYNC
CONTROL
D3 (4/6) BA7078AF-E2 (IC1809)
16
1
15 14 13 12
VCC 1 REXT/CEXT CEXT 1 1 Q 2Q 2 CLR 2B 2A
1A 1B
1 CLR
1Q 2Q
CEXT 2
2 REXT/CEXT
GND
11 10 9
2 3 4 5 6 7 8
CLR
Q
Q
CLR
Q
Q
D3 (4/6) TC74HC123AF(EL) (IC1807)
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
VCC 4B 4A 4Y 3B 3A
1A 1B 1Y 2A 2B 2Y
3Y
D3 (4/6) TC74LCX00FT(EL) (IC1801)
GND
V
DD
1 2 3 4 5 6 7
14 13 12 11 10 9 8
D3 (4/6) TC74LCX14F(EL) (IC1800)
D3 D3
D3 (3/6) NJM2903V (TE2) (IC2403)
6
7
5
8
2
2
1
3
4
1
OUTPUT1
_
INPUT1
+
INPUT1
GND
V
+
OUTPUT2
_
INPUT2
+
INPUT2