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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

111

Revision 1.4 (08-19-08)

DATASHEET

8.4.9

TX Data FIFO Direct PIO Writes

In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished
by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host
processor must increment its address when accessing the LAN9312.

Timing is identical to a PIO write, and the FIFO_SEL and END_SEL signals have the same timing
characteristics as the address lines. A TX Data FIFO direct PIO write cycle begins when both nCS and
nWR are asserted. Either or both of these control signals must de-assert between cycles for the period
specified in

Table 15.13, “TX Data FIFO Direct PIO Write Cycle Timing Values,” on page 451

. The cycle

ends when either or both nCS and nWR are de-asserted. They may be asserted and de-asserted in
any order. The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in

.

Note:

A[9:3] are ignored during TX Data FIFO direct PIO writes.

Please refer to

Section 15.5.9, "TX Data FIFO Direct PIO Write Cycle Timing," on page 451

for the AC

timing specifications for TX Data FIFO direct PIO write operations.

8.5

HBI Interrupts

The HBI allows access to all interrupt configuration and status registers within the LAN9312. The
LAN9312 implements a multi-tier interrupt hierarchy with the

Interrupt Configuration Register

,

Interrupt Status Register (INT_STS)

, and

Interrupt Enable Register (INT_EN)

at the top

level. These registers allow for the configuration of which interrupts trigger the IRQ, as well as the IRQ
deassertion and polarity properties. Interrupts may be generated from the 1588 Timestamping, Switch
Fabric, Port 1 PHY, Port 2 PHY, Host MAC, EEPROM Loader, General Purpose Timer, General
Purpose I/O, and Power Management blocks.

For more information of the LAN9312 interrupts, refer to

Chapter 5, System Interrupts

.

Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation

VALID

D[31:0] (INPUT)

nCS, nWR

A[x:3]

VALID

END_SEL

VALID

A[2]

FIFO_SEL

(WRITE DATA TO TX DATA FIFO)

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Summary of Contents for LAN9312

Page 1: ... address Switch Management Port mirroring monitoring sniffing ingress and or egress traffic on any ports or port pairs Fully compliant statistics MIB gathering counters Control registers configurable on the fly Ports 2 internal 10 100 PHYs with HP Auto MDIX support Fully compliant with IEEE 802 3 standards 10BASE T and 100BASE TX support Full and half duplex support Full duplex flow control Backpr...

Page 2: ...e Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe propert...

Page 3: ...28 VTQFP Pin Diagram 26 3 1 2 128 XVTQFP Pin Diagram 27 3 2 Pin Descriptions 28 Chapter 4 Clocking Resets and Power Management 36 4 1 Clocks 36 4 2 Resets 36 4 2 1 Chip Level Resets 37 4 2 1 1 Power On Reset POR 37 4 2 1 2 nRST Pin Reset 38 4 2 2 Multi Module Resets 38 4 2 2 1 Digital Reset DIGITAL_RST 38 4 2 2 2 Soft Reset SRST 39 4 2 3 Single Module Resets 39 4 2 3 1 Port 2 PHY Reset 39 4 2 3 2 ...

Page 4: ...67 6 4 3 1 Port Default Priority 69 6 4 3 2 IP Precedence Based Priority 69 6 4 3 3 DIFFSERV Based Priority 69 6 4 3 4 VLAN Priority 69 6 4 4 VLAN Support 70 6 4 5 Spanning Tree Support 70 6 4 6 Ingress Flow Metering and Coloring 71 6 4 6 1 Ingress Flow Calculation 72 6 4 7 Broadcast Storm Control 74 6 4 8 IPv4 IGMP IPv6 MLD Support 74 6 4 9 Port Mirroring 75 6 4 10 Host CPU Port Special Tagging 7...

Page 5: ... 95 7 2 9 2 PHY Energy Detect Power Down 95 7 2 10 PHY Resets 95 7 2 10 1 PHY Software Reset via RESET_CTL 95 7 2 10 2 PHY Software Reset via PHY_BASIC_CTRL_x 96 7 2 10 3 PHY Power Down Reset 96 7 2 11 LEDs 96 7 2 12 Required Ethernet Magnetics 96 7 3 Virtual PHY 96 7 3 1 Virtual PHY Auto Negotiation 96 7 3 1 1 Parallel Detection 97 7 3 1 2 Disabling Auto Negotiation 97 7 3 1 3 Virtual PHY Pause F...

Page 6: ...s 128 9 8 6 1 TX Example 1 128 9 8 6 2 TX Example 2 130 9 8 7 Transmitter Errors 131 9 8 8 Stopping and Starting the Transmitter 131 9 9 RX Data Path Operation 132 9 9 1 RX Slave PIO Operation 132 9 9 1 1 Receive Data FIFO Fast Forward 134 9 9 1 2 Force Receiver Discard Receiver Dump 134 9 9 2 RX Packet Format 134 9 9 3 RX Status Format 135 9 9 4 Stopping and Starting the Receiver 136 9 9 5 Receiv...

Page 7: ...terrupt Polarity 163 13 2 2 2 IEEE 1588 GPIO Interrupts 164 13 3 LED Operation 164 Chapter 14 Register Descriptions 166 14 1 TX RX FIFO Ports 167 14 1 1 TX RX Data FIFO s 167 14 1 2 TX RX Status FIFO s 167 14 1 3 Direct FIFO Access Mode 167 14 2 System Control and Status Registers 168 14 2 1 Interrupts 172 14 2 1 1 Interrupt Configuration Register IRQ_CFG 172 14 2 1 2 Interrupt Status Register INT...

Page 8: ...9 14 2 6 2 Port 2 Manual Flow Control Register MANUAL_FC_2 231 14 2 6 3 Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII 233 14 2 6 4 Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA 235 14 2 6 5 Switch Fabric CSR Interface Command Register SWITCH_CSR_CMD 236 14 2 6 6 Switch Fabric MAC Address High Register SWITCH_MAC_ADDRH 238 14 2 6 7 Switch Fabric MAC Address Low Register SWI...

Page 9: ...2 19 Port x MAC Receive Packet Length Count Register MAC_RX_PKTLEN_CNT_x 340 14 5 2 20 Port x MAC Receive Good Packet Length Count Register MAC_RX_GOODPKTLEN_CNT_x 341 14 5 2 21 Port x MAC Receive Symbol Error Count Register MAC_RX_SYMBOL_CNT_x 342 14 5 2 22 Port x MAC Receive Control Frame Count Register MAC_RX_CTLFRM_CNT_x 343 14 5 2 23 Port x MAC Transmit Configuration Register MAC_TX_CFG_x 344...

Page 10: ...ffer Manager Flow Control Pause Level Register BM_FC_PAUSE_LVL 413 14 5 4 4 Buffer Manager Flow Control Resume Level Register BM_FC_RESUME_LVL 414 14 5 4 5 Buffer Manager Broadcast Buffer Level Register BM_BCST_LVL 415 14 5 4 6 Buffer Manager Port 0 Drop Count Register BM_DRP_CNT_SRC_MII 416 14 5 4 7 Buffer Manager Port 1 Drop Count Register BM_DRP_CNT_SRC_1 417 14 5 4 8 Buffer Manager Port 2 Drop...

Page 11: ...itch with 32 Bit Non PCI CPU Interface Datasheet SMSC LAN9312 11 Revision 1 4 08 19 08 DATASHEET 15 6 Clock Circuit 453 Chapter 16 Package Outlines 454 16 1 128 VTQFP Package Outline 454 16 2 128 XVTQFP Package Outline 456 Chapter 17 Revision History 458 ...

Page 12: ...Big Endian Byte Ordering 100 Figure 8 3 Functional Timing for PIO Read Operation 106 Figure 8 4 Functional Timing for PIO Burst Read Operation 107 Figure 8 5 Functional Timing for RX Data FIFO Direct PIO Read Operation 108 Figure 8 6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation 109 Figure 8 7 Functional Timing for PIO Write Operation 110 Figure 8 8 Functional Timing for TX Da...

Page 13: ...IO Read Cycle Timing 446 Figure 15 5 PIO Burst Read Cycle Timing 447 Figure 15 6 RX Data FIFO Direct PIO Read Cycle Timing 448 Figure 15 7 RX Data FIFO Direct PIO Burst Read Cycle Timing 449 Figure 15 8 PIO Write Cycle Timing 450 Figure 15 9 TX Data FIFO Direct PIO Write Cycle Timing 451 Figure 15 10Microwire Timing 452 Figure 16 1 LAN9312 128 VTQFP Package Definition 454 Figure 16 2 LAN9312 128 V...

Page 14: ...8 2 Read After Read Timing Rules 105 Table 9 1 Address Filtering Modes 115 Table 9 2 Wake Up Frame Filter Register Structure 117 Table 9 3 Filter i Byte Mask Bit Definitions 117 Table 9 4 Filter i Command Bit Definitions 117 Table 9 5 Filter i Offset Bit Definitions 118 Table 9 6 Filter i CRC 16 Bit Definitions 118 Table 9 7 EEPROM Byte Ordering and Register Correlation 119 Table 9 8 TX RX FIFO Co...

Page 15: ... 307 Table 14 13Metering Color Table Register Descriptions 395 Table 15 1 Supply and Current 10BASE T Full Duplex 441 Table 15 2 Supply and Current 100BASE TX Full Duplex 441 Table 15 3 I O Buffer Characteristics 442 Table 15 4 100BASE TX Transceiver Characteristics 442 Table 15 5 10BASE T Transceiver Characteristics 443 Table 15 6 nRST Reset Pin Timing Values 444 Table 15 7 Power On Configuration...

Page 16: ...rs added to the end of an Ethernet frame used for error detection and correction FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I O HBI Host Bus Interface The physical bus connecting the LAN9312 to the host Also referred to as the Host Bus HBIC Host Bus Interface Controller The hardware module that interfaces the LAN9312 to the HBI Host External system Includes proces...

Page 17: ...ionally Unique Identifier Outbound Refers to data output from the LAN9312 to the host PIO cycle Program I O cycle An SRAM like read or write cycle on the HBI PISO Parallel In Serial Out PLL Phase Locked Loop PTP Precision Time Protocol RESERVED Refers to a reserved bit field or address Unless otherwise noted reserved bits must always be zero for write operations Unless otherwise noted values are n...

Page 18: ...ted in the pin description internal pull ups are always enabled Note Internal pull up resistors prevent unconnected inputs from floating Do not rely on internal resistors to drive signals external to the LAN9312 When connected to a load that must be pulled high an external resistor must be added PD 50uA typical internal pull down Unless otherwise noted in the pin description internal pull downs ar...

Page 19: ...as no effect WAC Write Anything to Clear writing anything clears the value RC Read to Clear Contents is cleared after the read Writes have no effect LL Latch Low Clear on read of register LH Latch High Clear on read of register SC Self Clearing Contents are self cleared after the being set Writes of zero have no effect Contents can be read SS Self Setting Contents are self setting after being clea...

Page 20: ... the LAN9312 switch fabric to the host bus interface All ports support automatic or manual full duplex flow control or half duplex backpressure forced collision flow control Automatic 32 bit CRC generation checking and automatic payload padding are supported to further reduce CPU overhead 2K jumbo packet 2048 byte support allows for oversized packet transfers effectively increasing throughput whil...

Page 21: ... PHY Registers 10 100 PHY Registers Switch Registers CSRs IEEE 1588 Time Stamp IEEE 1588 Time Stamp Switch Fabric GPIO LED Controller Dynamic QoS 4 Queues Dynamic QoS 4 Queues Dynamic QoS 4 Queues Switch Engine Buffer Manager Search Engine Frame Buffers IEEE 1588 Time Stamp Clock Events MII MDIO MII MDIO To optional GPIOs LEDs To Ethernet To Ethernet LAN9312 Host Bus Interface TX RX FIFOs Host MAC...

Page 22: ...L or Reset bit 15 in the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x Resets the Port 2 PHY Port 1 PHY Reset PHY1_RST bit 1 in the Reset Control Register RESET_CTL or Reset bit 15 in the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x Resets the Port 1 PHY Virtual PHY Reset VPHY_RST bit 0 in the Reset Control Register RESET_CTL bit 10 in the Power Management Control Register PMT_CTR...

Page 23: ... of the switch fabric 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed Each port is allocated 1a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic effectively utilizing all available memory This memory is managed dynamically via the Buffer Manager block Switch CSRs This block contains all switch related...

Page 24: ...xternal EEPROM with the system register bus and the EEPROM Loader Multiple types I2 C Microwire and sizes of external EEPROMs are supported Configuration of the EEPROM type and size are accomplished via the eeprom_type_strap and eeprom_size_strap 1 0 configuration straps respectively Various commands are supported for each EEPROM type allowing for the storage and retrieval of static data The I2 C ...

Page 25: ...312 Host Bus Interface HBI is connected to the host microprocessor microcontroller via the asynchronous 32 bit interface allowing access to the LAN9312 system configuration and status registers The LAN9312 utilizes the internal Host MAC to provide a network path for the host CPU The LAN9312 may share the host bus with additional system memory and or peripherals For more information on the HBI refe...

Page 26: ... VDD33IO D6 D5 D8 D7 VDD33IO EEDI EE_SDA NC NC nP1LED0 GPIO0 VDD33IO nP1LED2 GPIO2 nP1LED1 GPIO1 VDD18CORE nP1LED3 GPIO3 nP2LED0 GPIO4 VDD33IO nP2LED2 GPIO6 nP2LED1 GPIO5 GPIO8 nP2LED3 GPIO7 VSS VDD33IO GPIO10 GPIO9 NC GPIO11 VDD18CORE TEST1 VDD33IO VDD33IO AUTO_MDIX_2 nRST PHY_ADDR_SEL AUTO_MDIX_1 VDD33IO LED_EN VDD18CORE NC VDD18CORE NC D30 D31 VDD33IO D29 D27 D28 D25 D26 VDD33IO D24 D23 VDD18CO...

Page 27: ... D3 D4 VDD33IO D6 D5 D8 D7 VDD33IO EEDI EE_SDA NC NC nP1LED0 GPIO0 VDD33IO nP1LED2 GPIO2 nP1LED1 GPIO1 VDD18CORE nP1LED3 GPIO3 nP2LED0 GPIO4 VDD33IO nP2LED2 GPIO6 nP2LED1 GPIO5 GPIO8 nP2LED3 GPIO7 VSS VDD33IO GPIO10 GPIO9 NC GPIO11 VDD18CORE TEST1 VDD33IO VDD33IO AUTO_MDIX_2 nRST PHY_ADDR_SEL AUTO_MDIX_1 VDD33IO LED_EN VDD18CORE NC VDD18CORE NC D30 D31 VDD33IO D29 D27 D28 D25 D26 VDD33IO D24 D23 V...

Page 28: ... 9 8 bits General Purpose I O Data GPIO 3 0 IS O12 OD12 PU General Purpose I O Data When configured as GPIO via the LED Configuration Register LED_CFG these general purpose signals are fully programmable as either push pull outputs open drain outputs or Schmitt triggered inputs by writing the General Purpose I O Configuration Register GPIO_CFG and General Purpose I O Data Direction Register GPIO_D...

Page 29: ... either push pull outputs open drain outputs or Schmitt triggered inputs by writing the General Purpose I O Configuration Register GPIO_CFG and General Purpose I O Data Direction Register GPIO_DATA_DIR The pull ups are enabled in GPIO mode The input buffers are disabled when set as an output Note See Chapter 13 GPIO LED Controller on page 162 for additional details 127 Port 2 Ethernet TX Negative ...

Page 30: ...nnected directly to the VDD18TX2 pin for proper operation Refer to the LAN9312 application note for additional connection information Table 3 4 Host Bus Interface Pins PIN NAME SYMBOL BUFFER TYPE DESCRIPTION 4 6 8 12 15 17 19 20 22 26 28 32 34 38 41 44 Host Bus Data D 31 0 IS O8 Host Bus Data High Bits 31 0 of the Host Bus 32 bit data port Note Big and little endianess is supported 45 47 49 53 55 ...

Page 31: ...EPROM mode EEPROM_TYPE 0 this pin is the Microwire EEPROM serial data input EEPROM I2 C Serial Data Input Output EE_SDA IS OD8 EEPROM I2 C Serial Data Input Output EE_SDA In I2 C EEPROM mode EEPROM_TYPE 1 this pin is the I2 C EEPROM serial data input output 98 EEPROM Microwire Data Output EEDO O8 EEPROM Microwire Data Output In Microwire EEPROM mode EEPROM_TYPE 0 this pin is the Microwire EEPROM s...

Page 32: ...put Note In I2 C mode EEPROM_TYPE 1 this pin is not used and is driven low EEPROM Size Strap 0 EEPROM_SIZE_0 IS Note 3 3 EEPROM Size Strap 0 Configures the low bit of the EEPROM size range as specified in Section 10 2 I2C Microwire Master EEPROM Controller on page 137 See Note 3 4 Table 3 6 Dedicated Configuration Strap Pins PIN NAME SYMBOL BUFFER TYPE DESCRIPTION 67 LED Enable Strap LED_EN IS PU ...

Page 33: ...Data GPIO 11 8 IS OD12 O12 PU Note 3 7 General Purpose I O Data These general purpose signals are fully programmable as either push pull outputs open drain outputs or Schmitt triggered inputs by writing the General Purpose I O Configuration Register GPIO_CFG and General Purpose I O Data Direction Register GPIO_DATA_DIR For more information refer to Chapter 13 GPIO LED Controller on page 162 Note T...

Page 34: ... P PLL 1 8V Power Supply This pin must be connected to VDD18CORE for proper operation Refer to the LAN9312 application note for additional connection information 105 Crystal Input XI ICLK Crystal Input External 25MHz crystal input This signal can also be driven by a single ended clock oscillator When this method is used XO should be left unconnected 106 Crystal Output XO OCLK Crystal Output Extern...

Page 35: ...pad for 128 XVTQFP package only 18 48 80 97 112 113 128 Note 3 8 Common Ground VSS P Common Ground Table 3 10 No Connect Pins PIN NAME SYMBOL BUFFER TYPE DESCRIPTION 1 2 56 76 94 95 102 103 109 No Connect NC No Connect These pins must be left floating for normal device operation Table 3 9 Core and I O Power and Ground Pins continued PIN NAME SYMBOL BUFFER TYPE DESCRIPTION ...

Page 36: ...e Running Clock on page 161 for additional details Note Crystal specifications are provided in Table 15 15 LAN9312Crystal Specifications on page 453 4 2 Resets The LAN9312 provides multiple hardware and software reset sources which allow varying levels of the LAN9312 to be reset All resets can be categorized into three reset types as described in the following sections Chip Level Resets Power On R...

Page 37: ...cessed With the exception of the Hardware Configuration Register HW_CFG Power Management Control Register PMT_CTRL Byte Order Test Register BYTE_TEST and Reset Control Register RESET_CTL read access to any internal resources is forbidden while the READY bit is cleared Writes to any address are invalid until the READY bit is set Note The LAN9312 must be read at least once after any chip level reset...

Page 38: ...t do not reset the entire chip Configuration straps are not latched upon multi module resets A multi module reset is initiated by assertion of the following Digital Reset DIGITAL_RST Soft Reset SRST Chip level reset completion configuration can be determined by polling the READY bit of the Hardware Configuration Register HW_CFG or Power Management Control Register PMT_CTRL until it is set When set...

Page 39: ...g from a PHY power down mode This reset differs in that the PHY power down mode reset does not reload or reset any of the PHY registers Refer to Section 7 2 9 PHY Power Down Modes on page 94 for additional information Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the Reset Control Register RESET_CTL or the Reset bit in the Port x PHY Basic Control Register PHY_BASIC_...

Page 40: ...en unconnected If a particular configuration strap is connected to a load an external pull up or pull down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching The internal resistor can also be overridden by the addition of an external resistor Note The system designer must guarantee that configuration strap pins meet the t...

Page 41: ...IXCTL bit in the Port x PHY Special Control Status Indication Register PHY_SPECIAL_CONTROL_STAT_IND_x is cleared When configured low Auto MDIX is disabled When configured high Auto MDIX is enabled Note If AMDIXCTL is set this strap had no effect AUTO_MDIX_1 manual_mdix_strap_1 Port 1 Manual MDIX Strap Configures MDI 0 or MDIX 1 for Port 1 when the auto_mdix_strap_1 is low and the AMDIXCTL bit of t...

Page 42: ...s selected This strap also affects the default value of the following bits PHY_DUPLEX bit of the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x 10BASE T Full Duplex bit 6 of the Port x PHY Auto Negotiation Advertisement Register PHY_AN_ADV_x MODE 2 0 bits of the Port x PHY Special Modes Register PHY_SPECIAL_MODES_x Refer to the respective register definition sections for additional informat...

Page 43: ...PHY_SPECIAL_CONTROL_STAT_IND_x is cleared When configured low Auto MDIX is disabled When configured high Auto MDIX is enabled Note If AMDIXCTL is set this strap had no effect AUTO_MDIX_2 manual_mdix_strap_2 Port 2 Manual MDIX Strap Configures MDI 0 or MDIX 1 for Port 2 when the auto_mdix_strap_2 is low and the AMDIXCTL bit of the Port x PHY Special Control Status Indication Register PHY_SPECIAL_CO...

Page 44: ...s selected This strap also affects the default value of the following bits PHY_DUPLEX bit of the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x 10BASE T Full Duplex bit 6 of the Port x PHY Auto Negotiation Advertisement Register PHY_AN_ADV_x MODE 2 0 bits of the Port x PHY Special Modes Register PHY_SPECIAL_MODES_x Refer to the respective register definition sections for additional informat...

Page 45: ...Port 0 Host MAC Backpressure Enable Strap Configures the default value for the Port 0 Backpressure Enable BP_EN_MII bit of the Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII When configured low backpressure is disabled When configured high backpressure is enabled 1b FD_FC_strap_mii Port 0 Host MAC Full Duplex Flow Control Enable Strap Configures the default of the TX_FC_MII and RX_FC_M...

Page 46: ...esults together to generate the PME_INT status bit in the Interrupt Status Register INT_STS The PME_INT status bit is then masked with the PME_EN bit and conditioned before becoming the PME output pin The PME output characteristics can be configured via the PME_TYPE PME_IND and PME_POL bits of the Power Management Control Register PMT_CTRL These bits allow the PME to be open drain active high push...

Page 47: ...gger the IRQ interrupt output pin as described in Section 5 2 3 Ethernet PHY Interrupts on page 52 Refer to Section 7 2 9 2 PHY Energy Detect Power Down on page 95 for details on the operation and configuration of the PHY energy detect power down mode Figure 4 1 PME and PME_INT Signal Generation PME ED_EN1 bit 14 of PMT_CTRL register WOL_EN bit 9 of PMT_CTRL register 50ms PME_EN bit 1 of PMT_CTRL ...

Page 48: ...a the WUEN bit for wake up frames and the MPEN bit for magic packets detection of wake up frames or magic packets causes the WUFR and MPR bits of the HMAC_WUCSR register to set respectively If either of the WUFR and MPR bits are set the WOL_STS bit of the Power Management Control Register PMT_CTRL will be set These events can enable PME output assertion by additionally setting the PME_EN bit of th...

Page 49: ...T_EN and Interrupt Configuration Register IRQ_CFG The Interrupt Status Register INT_STS and Interrupt Enable Register INT_EN aggregate and enable disable all interrupts from the various LAN9312 sub modules combining them together to create the IRQ interrupt These registers provide direct interrupt access configuration to the Host MAC General Purpose Timer software and device ready interrupts These...

Page 50: ..._INT2 of INT_STS register PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 Port 1 PHY Interrupt Registers Bit 26 PHY_INT1 of INT_STS register SW_IMR SW_IPR Switch Fabric Interrupt Registers Bit 28 SWITCH_INT of INT_STS register BM_IMR BM_IPR Buffer Manager Interrupt Registers Bit 6 BM of SW_IPR register SWE_IMR SWE_IPR Switch Engine Interrupt Registers Bit 5 SWE of SW_IPR register MAC_IMR_ 2 1 MII MAC_...

Page 51: ...ccurred in the Switch Engine Interrupt Pending Register SWE_IPR In turn the Switch Engine Interrupt Pending Register SWE_IPR and Switch Engine Interrupt Mask Register SWE_IMR provide status and enabling disabling of all Switch Fabric sub modules interrupts Buffer Manager Switch Engine and Port 2 1 0 MACs The low level Switch Fabric sub module interrupt pending and mask registers of the Buffer Mana...

Page 52: ...ter INT_EN must be set and IRQ output must be enabled via bit 8 IRQ_EN of the Interrupt Configuration Register IRQ_CFG For additional details on the Ethernet PHY interrupts refer to Section 7 2 8 1 PHY Interrupts on page 94 5 2 4 GPIO Interrupts Each GPIO 11 0 of the LAN9312 is provided with its own interrupt The top level GPIO bit 12 of the Interrupt Status Register INT_STS provides indication th...

Page 53: ...nt conditions These include energy detect on the Port 1 2 PHYs and Wake On LAN wake up frame or magic packet detection by the Host MAC In order for a Power Management interrupt event to trigger the external IRQ interrupt pin the desired Power Management interrupt event must be enabled in the Power Management Control Register PMT_CTRL bits 15 14 and or 9 bit 17 PME_INT_EN of the Interrupt Enable Re...

Page 54: ...oftware to generate an interrupt and is designed for general software usage 5 2 9 Device Ready Interrupt A device ready interrupt is provided in the top level Interrupt Status Register INT_STS and Interrupt Enable Register INT_EN The READY interrupt bit 30 of the Interrupt Status Register INT_STS indicates that the LAN9312 is ready to be accessed after a power up or reset condition Writing a 1 to ...

Page 55: ... in the switch fabric which provide basic 10 100 Ethernet functionality for each switch fabric port Switch Engine SWE This block is the core of the switch fabric and provides VLAN layer 2 switching for all three switch ports Buffer Manager BM This block provides control of the free buffer space transmit queues and scheduling Refer to Figure 2 1 Internal LAN9312 Block Diagram on page 21 for details...

Page 56: ...iated by writing the desired data into the Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA The completion of the write cycle is indicated by the clearing of the CSR_BUSY bit at which time the address in the Switch Fabric CSR Interface Command Register SWITCH_CSR_CMD is incremented or decremented accordingly The user may then initiate a subsequent write cycle by writing the desired data i...

Page 57: ...to decrement AUTO_DEC bit set the CSR_ADDRESS field written with the desired register address and the R_nW bit set The completion of a read cycle is indicated by the clearing of the CSR_BUSY bit at which time the data can be read from the Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA When the data is read the address in the Switch Fabric CSR Interface Command Register SWITCH_CSR_CMD is...

Page 58: ... Manual Flow Control Register MANUAL_FC_2 or Port 0 Host MAC Manual Flow Control Register MANUAL_FC_MII Table 6 1 details the switch fabric flow control enable logic When in half duplex mode the transmit flow control back pressure enable is determined directly by the BP_EN_x bit of the ports manual flow control register When Auto negotiation is disabled or the MANUAL_FC_x bit of the ports manual f...

Page 59: ...egotiation Advertisement Register PHY_AN_ADV_x and Port x PHY Auto Negotiation Link Partner Base Page Ability Register PHY_AN_LP_BASE_ABILITY_x For the Virtual PHY these are the local partner swapped outputs from the bits in the Virtual PHY Auto Negotiation Advertisement Register VPHY_AN_ADV and Virtual PHY Auto Negotiation Link Partner Base Page Ability Register VPHY_AN_LP_BASE_ABILITY Refer to S...

Page 60: ...me Delimiter SFD The receive MAC checks the FCS the MAC Control Type and the byte count against the drop conditions The packet is stored in the RX FIFO as it is received The receive MAC determines the validity of each received packet by checking the Type field FCS and oversize or undersize conditions All bad packets will be either immediately dropped or marked at the end as bad packets Oversized p...

Page 61: ...Indirectly Accessible Switch Control and Status Registers on page 307 and Section 14 5 2 3 through Section 14 5 2 22 for detailed descriptions of these counters Total undersized packets Section 14 5 2 3 on page 324 Total packets 64 bytes in size Section 14 5 2 4 on page 325 Total packets 65 through 127 bytes in size Section 14 5 2 5 on page 326 Total packets 128 through 255 bytes in size Section 1...

Page 62: ...ngine The FIFO logic manages the re transmission for normal collision conditions or discards the frames for late or excessive collisions When in full duplex mode the transmit MAC uses the flow control algorithm specified in IEEE 802 3 MAC pause frames are used primarily for flow control packets which pass signalling information between stations MAC pause frames have a unique type of 8808h and a pa...

Page 63: ... provides packet metering for input rate control It also implements port mirroring broadcast throttling and multicast pruning and filtering Packet priorities are supported based on the IPv4 TOS bits and IPv6 Traffic Class bits using a DIFFSERV Table mapping the non DIFFSERV mapped IPv4 precedence bits VLAN priority using a per port Priority Regeneration Table DA based static priority and Traffic C...

Page 64: ...Multicast Pruning The destination port that is returned as a result of a destination MAC address lookup may be a single port or any combination of ports The latter is used to setup multicast address groups An entry with a multicast MAC address would be entered manually by the host CPU with the appropriate destination port s Typically the Static bit should also be set to prevent automatic aging of ...

Page 65: ...R Read Data 0 Register SWE_ALR_RD_DAT_0 and Switch Engine ALR Read Data 1 Register SWE_ALR_RD_DAT_1 Note The entries read are not necessarily in the same order as they were learned or manually added The following procedure should be followed in order to read the ALR entries 1 Write the Switch Engine ALR Command Register SWE_ALR_CMD with 0002h Get First Entry 2 Write the Switch Engine ALR Command R...

Page 66: ...Drop on Red is set and the packet is colored Red it is discarded If the destination address was not found in the ALR table an unknown or a broadcast and the Broadcast Buffer Level is exceeded the packet is discarded If there is insufficient buffer space the packet is discarded When the switch is enabled for VLAN support these following rules also apply If the packet is untagged or priority tagged ...

Page 67: ...Priority Regeneration table the port default The last four options listed are sent through the Traffic Class table which maps the selected priority to one of the four output queues The static value from the ALR table directly specifies the queue Figure 6 4 Switch Engine Transmit Queue Selection priority calculation programmable DIFFSERV table programmable port default table programmable Priority R...

Page 68: ... the configuration bits Figure 6 5 Switch Engine Transmit Queue Calculation Queue ALR Priority DA Highest Priority ALR Static Bit Y Y Resolved Priority Priority Regen VLAN Priority N Packet is IPv4 v6 Use IP Resolved Priority IP Precedence Y Use Precedence Y N Resolved Priority DIFFSERV TC N N Y VLAN Enable Packet is Tagged Y N N Resolved Priority Default Priority Source Port wait for ALR result Q...

Page 69: ...f the IPv4 TOS octet or the IPv6 Traffic Class octet and is used as an index into the DIFFSERV table The output of the DIFFSERV table is then used as the priority This priority is then passed through the Traffic Class table to select the transmit priority queue Note The DIFFSERV table is not initialized upon reset or power up If DIFFSERV is enabled then the full table must be initialized by the ho...

Page 70: ...tructions are used at egress on ports defined as hybrid ports Refer to Section 14 5 3 8 on page 375 through Section 14 5 3 11 on page 378 for detailed VLAN register descriptions 6 4 5 Spanning Tree Support Hardware support for the Spanning Tree Protocol STP and the Rapid Spanning Tree Protocol RSTP includes a per port state register as well as the override bit in the MAC Address Table entries Sect...

Page 71: ...tream First the Committed Burst bucket is incremented up to the maximum set by the CBS Once the Committed Burst bucket is full the Excess Burst bucket is incremented up to the maximum set by the EBS The CIR rate is specified in time per byte The value programmed is in approximately 20 nS per byte increments Typical values are listed in Table 6 3 When a port is receiving at 10Mbps any setting faste...

Page 72: ...iting the maximum value of the token buckets Refer to Section 14 5 3 25 on page 393 through Section 14 5 3 29 on page 398 for detailed register descriptions 6 4 6 1 Ingress Flow Calculation Based on the flow monitoring mode an ingress flow definition can include the ingress priority This is calculated similarly to the transmit queue with the exception that the Priority Regeneration and the Traffic...

Page 73: ...rt Default Table 3b 3b 2b 6b 3b Packet is Tagged VL Higher Priority Packet is IPv4 Packet is IP Use Precedence Use IP IPv4 TOS IPv6 TC flow priority Source Port VLAN Priority IPv4 Precedence 3b 3b VLAN Enable Priority Calculation Packet is from Host Flow Priority VLAN Priority N Packet is IPv4 v6 Use IP Flow Priority IP Precedence Y Use Precedence Y N Flow Priority DIFFSERV TC N Y Vlan Enable Pack...

Page 74: ...multicast packets are trapped and redirected to the MLD IGMP snoop port typically set to the port to which the host CPU is connected IGMP packets are identified as IPv4 packets with a protocol of 2 Both Ethernet and IEEE 802 3 frame formats are supported as are VLAN tagged packets On ingress if MLD packet snooping is enabled in the Switch Engine Global Ingress Configuration Register SWE_GLOBAL_ING...

Page 75: ...that are forwarded to a port designated as a mirrored port are also transmitted by the sniffer port For example Port 2 is setup to be a mirrored port and Port 0 is setup to be the sniffer port If a packet is received on Port 1 with a destination of Port 2 it is forwarded to both Port 2 and Port 0 Note A packet will never be transmitted out of the receiving port A receive packet is not normally mir...

Page 76: ...ossible for a normally tagged maximum size incoming packet to become 1526 bytes in length In order for the Host MAC to receive this length packet without indicating a length error the Host MAC VLAN2 Tag Register HMAC_VLAN2 in the Host MAC should be set to 8100h and the Host MAC VLAN1 Tag Register HMAC_VLAN1 should be set to a value other than 8100h This configuration will allow frames up to 1538 b...

Page 77: ...l Register BM_BCST_LVL and if the configured drop level is reached or exceeded subsequent packets are dropped 6 5 2 Random Early Discard RED Based on the ingress flow monitoring detailed in Section 6 4 6 Ingress Flow Metering and Coloring on page 71 packets are colored as Green Yellow or Red Packets colored Red are always discarded if the Drop on Red bit in the Buffer Manager Configuration Registe...

Page 78: ...rate limiting occurs before the Transmit Priority Queue Servicing such that a lower priority queue will be serviced if a higher priority queue is being rate limited The egress limiting is enabled per priority queue After a packet is selected to be sent its length is recorded The switch then waits a programmable amount of time scaled by the packet length before servicing that queue once again The a...

Page 79: ...e ingress port number The entry in the VLAN table is either the VLAN from the received packet or the ingress ports default VID When a received packet is non tagged a new VLAN tag is added if two conditions are met First the Insert Tag bit for the egress port in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE must be set Second the un tag instruction associated with the ingress port...

Page 80: ...ag Bit Y Non tagged Y Add Tag VID Default VID ingress_port Priority Default Priority ingress_port Y Send Packet Untouched N Priority Tagged Default VID ingress_port Un tag Bit Y Strip Tag N Normal Tagged Received VID Un tag Bit Y Strip Tag Change Tag egress_port N N Send Packet Untouched Y Change Priority egress_port Modify Tag VID Default VID ingress_port Priority Default Priority ingress_port N ...

Page 81: ... port that contains the number of packets dropped due solely to ingress rate limit discarding Red and random Yellow dropping This count value can be subtracted from the drop counter as described above to obtain the drop counts due solely to buffer space limits The ingress rate drop counters are accessible via the following registers Buffer Manager Port 0 Ingress Rate Drop Count Register BM_RATE_DR...

Page 82: ...ister set and can be configured indirectly via the Host MAC or directly via the memory mapped Virtual PHY registers Refer to Section 14 4 Ethernet PHY Control and Status Registers for details on the Ethernet PHY registers The LAN9312 Ethernet PHYs are discussed in detail in the following sections Section 7 2 Port 1 2 PHYs on page 83 Section 7 3 Virtual PHY on page 96 7 1 1 PHY Addressing Each indi...

Page 83: ...y PHY Wherever a lowercase x has been appended to a port or signal name it can be replaced with 1 or 2 to indicate the Port 1 or Port 2 PHY respectively All references to PHY in this section can be used interchangeably for both the Port 1 2 PHYs This nomenclature excludes the Virtual PHY A block diagram of the Port x PHYs main components can be seen in Figure 7 1 Figure 7 1 Port x PHY Block Diagra...

Page 84: ...ransmit data passes from the MII block to the 4B 5B Encoder This block encodes the data from 4 bit nibbles to 5 bit symbols known as code groups according to Table 7 2 Each 4 bit data nibble is mapped to 16 of the 32 possible code groups The remaining 16 code groups are either used for control information or are not valid The first 16 code groups are referred to by the hexadecimal values of their ...

Page 85: ...se MII Receive Error RXER Sent for rising MII Transmitter Enable signal TXEN 10001 K Second nibble of SSD translated to 0101 following J else MII Receive Error RXER Sent for rising MII Transmitter Enable signal TXEN 01101 T First nibble of ESD causes de assertion of CRS if followed by R else assertion of MII Receive Error RXER Sent for falling MII Transmitter Enable signal TXEN 00111 R Second nibb...

Page 86: ...l represents a code bit 0 7 2 1 5 100M Transmit Driver The MLT 3 data is then passed to the analog transmitter which drives the differential MLT 3 signal on output pins TXPx and TXNx where x is replaced with 1 for the Port 1 PHY or 2 for the Port 2 PHY to the twisted pair media across a 1 1 ratio isolation transformer The 10BASE T and 100BASE TX signals pass through the same transformer so that co...

Page 87: ...on caused by the physical channel magnetics connectors and CAT 5 cable The equalizer can restore the signal for any good quality CAT 5 cable between 1m and 150m If the DC content of the signal is such that the low frequency components fall below the low frequency pole of the isolation transformer then the droop characteristics of the transformer will become significant and Baseline Wander BLW on t...

Page 88: ... 4 bit data nibbles according to the 4B 5B table shown in Table 7 2 The translated data is presented on the internal MII RXD 3 0 signal lines to the switch fabric MAC The SSD J K is translated to 0101 0101 as the first 2 nibbles of the MAC preamble Reception of the SSD causes the PHY to assert the RXDV signal indicating that valid data is available on the RXD bus Successive valid code groups are t...

Page 89: ...nk partner The manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXPx and TXNx outputs where x is replaced with 1 for the Port 1 PHY or 2 for the Port 2 PHY 7 2 4 10BASE T Receive The 10BASE T receiver gets the Manchester encoded analog signal from the cable via the magnetics It recovers the receive...

Page 90: ...m for exchanging configuration information between two link partners and automatically selecting the highest performance mode of operation supported by both sides Auto negotiation is fully defined in clause 28 of the IEEE 802 3 specification and is enabled by setting bit 12 PHY_AN of the Port x PHY Basic Control Register PHY_BASIC_CONTROL_x The advertised capabilities of the PHY are stored in the ...

Page 91: ...mitted by an FLP burst is known as a Link Code Word These are defined fully in IEEE 802 3 clause 28 In summary the PHY advertises 802 3 compliance in its selector field the first 5 bits of the Link Code Word It advertises its technology ability according to the bits set in the Port x PHY Auto Negotiation Advertisement Register PHY_AN_ADV_x There are 4 possible matches of the technology abilities I...

Page 92: ...th legacy link partners If a link is formed via parallel detection then bit 0 in the Port x PHY Auto Negotiation Expansion Register PHY_AN_EXP_x is cleared to indicate that the link partner is not capable of auto negotiation If a fault occurs during parallel detection bit 4 of the Port x PHY Auto Negotiation Expansion Register PHY_AN_EXP_x is set The Port x PHY Auto Negotiation Link Partner Base P...

Page 93: ...X design The Auto MDIX function can be disabled through bit 15 AMDIXCTRL of the Port x PHY Special Control Status Indication Register PHY_SPECIAL_CONTROL_STAT_IND_x When AMDIXCTRL is cleared Auto MDIX can be selected via the auto_mdix_strap_x configuration strap The MDIX can also be configured manually via the manual_mdix_strap_x if both the AMDIXCTRL bit and the auto_mdix_strap_x configuration st...

Page 94: ...all PHY registers Refer to Section 14 4 2 Port 1 2 PHY Registers on page 285 for a list of all supported registers and register descriptions Non supported registers will be read as FFFFh 7 2 8 1 PHY Interrupts The PHY contains the ability to generate various interrupt events as described in Table 7 3 Reading the Port x PHY Interrupt Source Flags Register PHY_INTERRUPT_SOURCE_x shows the source of ...

Page 95: ...r down and asserts the INT7 interrupt bit 7 of the Port x PHY Interrupt Source Flags Register PHY_INTERRUPT_SOURCE_x The first and possibly second packet to activate ENERGYON may be lost When bit 13 EDPWRDOWN of the Port x PHY Mode Control Status Register PHY_MODE_CONTROL_STATUS_x is low energy detect power down is disabled The energy detect power down feature is part of the broader power manageme...

Page 96: ...2 so that an unmodified driver can be supported as if the Host MAC was attached to a single port PHY This functionality is designed to allow easy and quick integration of the LAN9312 into designs with minimal driver modifications The Virtual PHY provides a full bank of registers which comply with the IEEE 802 3 specification This enables the Virtual PHY to provide various status and control bits s...

Page 97: ...ex 10BASE T full duplex and 10BASE T half duplex in the Virtual PHY Auto Negotiation Link Partner Base Page Ability Register VPHY_AN_LP_BASE_ABILITY Neither the Virtual PHY or the emulated link partner support next page capability remote faults or 100BASE T4 If there is at least one common selection between the emulated link partner and the Virtual PHY advertised abilities then the auto negotiatio...

Page 98: ...Flow Control Register MANUAL_FC_MII This register allows the switch fabric port 0 flow control settings to be manually set when auto negotiation is disabled or the Manual Flow Control Select bit 0 is set The currently enabled duplex and flow control settings can also be monitored via this register The flow control values in the Virtual PHY Auto Negotiation Advertisement Register VPHY_AN_ADV are no...

Page 99: ...12 functions For a full list of all System CSR s and their descriptions refer to Section 14 2 System Control and Status Registers Interrupt support The HBI supports a variety of interrupt sources Individual interrupts can be monitored and enabled disabled via registers within the System CSRs for output on the IRQ pin For more information on interrupts refer to Chapter 5 System Interrupts on page 4...

Page 100: ...illustrated in Figure 8 1 Little Endian Byte Ordering and Figure 8 2 Big Endian Byte Ordering Figure 8 1 Little Endian Byte Ordering Figure 8 2 Big Endian Byte Ordering 32 BIT LITTLE ENDIAN END_SEL 0 0 1 2 3 0 1 2 3 0 7 8 15 16 23 31 24 0 7 8 15 16 23 31 24 MSB LSB INTERNAL ORDER HOST DATA BUS 32 BIT BIG ENDIAN END_SEL 1 0 1 2 3 0 7 8 15 16 23 31 24 3 2 1 0 0 7 8 15 16 23 31 24 MSB LSB HOST DATA B...

Page 101: ...reading the host control registers after any write cycle to the LAN9312 In some cases there is a delay between writing to the LAN9312 and the subsequent side effect change in the control register value For example when writing to the TX Data FIFO it takes up to 135ns for the level indication to change in the TX FIFO Information Register TX_FIFO_INF In order to prevent the host from reading stale d...

Page 102: ... Status FIFO 0 0 RX Status FIFO PEEK 0 0 TX Status FIFO 0 0 TX Status FIFO PEEK 0 0 ID_REV 0 0 IRQ_CFG 135 3 INT_STS 90 2 INT_EN 45 1 BYTE_TEST 0 0 FIFO_INT 45 1 RX_CFG 45 1 TX_CFG 45 1 HW_CFG 45 1 RX_DP_CTRL 45 1 RX_FIFO_INF 0 0 TX_FIFO_INF 135 3 PMT_CTRL 315 7 GPT_CFG 45 1 GPT_CNT 135 3 FREE_RUN 180 4 RX_DROP 0 0 MAC_CSR_CMD 45 1 MAC_CSR_DATA 45 1 AFC_CFG 45 1 1588_CLOCK_HI_RX_CAPTURE_1 0 0 1588...

Page 103: ...CK_LO_RX_CAPTURE_MII 0 0 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 0 0 1588_SRC_UUID_LO_RX_CAPTURE_MII 0 0 1588_CLOCK_HI_TX_CAPTURE_MII 0 0 1588_CLOCK_LO_TX_CAPTURE_MII 0 0 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII 0 0 1588_SRC_UUID_LO_TX_CAPTURE_MII 0 0 1588_CLOCK_HI_CAPTURE_GPIO_8 0 0 1588_CLOCK_LO_CAPTURE_GPIO_8 0 0 1588_CLOCK_HI_CAPTURE_GPIO_9 0 0 1588_CLOCK_LO_CAPTURE_GPIO_9 0 0 1588_CLOCK_HI 45 1 ...

Page 104: ... 45 1 LED_CFG 45 1 VPHY_BASIC_CTRL 45 1 VPHY_BASIC_STATUS 45 1 VPHY_ID_MSB 45 1 VPHY_ID_LSB 45 1 VPHY_AN_ADV 45 1 VPHY_AN_LP_BASE_ABILITY 45 1 VPHY_AN_EXP 45 1 VPHY_SPECIAL_CONTROL_STATUS 45 1 GPIO_CFG 45 1 GPIO_DATA_DIR 45 1 GPIO_INT_STS_EN 45 1 SWITCH_MAC_ADDRH 45 1 SWITCH_MAC_ADDRL 45 1 RESET_CTL 45 1 SWITCH_CSR_DIRECT_DATA NA NA Table 8 1 Read After Write Timing Rules continued REGISTER NAME M...

Page 105: ... being read Performing dummy reads of the Byte Order Test Register BYTE_TEST register is a convenient way to guarantee that the minimum wait time restriction is met Table 8 2 below also shows the number of dummy reads that are required for back to back read operations The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc 45ns For microprocessors with slower busses the...

Page 106: ...cle Timing Values on page 446 The cycle ends when either or both nCS and nRD are de asserted They may be asserted and de asserted in any order Read data is valid as indicated in the functional timing diagram in Figure 8 3 The endian select signal END_SEL has the same timing characteristics as the address lines Please refer to Section 15 5 4 PIO Read Cycle Timing on page 446 for the AC timing speci...

Page 107: ... The burst cycle ends when either or both nCS and nRD are de asserted They may be asserted and de asserted in any order Read data is valid as indicated in the functional timing diagram in Figure 8 4 Note Fresh data is supplied each time A 2 toggles The endian select signal END_SEL has the same timing characteristics as the upper address lines Please refer to Section 15 5 5 PIO Burst Read Cycle Tim...

Page 108: ...ddress lines An RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted Either or both of these control signals must de assert between cycles for the period specified in Table 15 10 RX Data FIFO Direct PIO Read Cycle Timing Values on page 448 The cycle ends when either or both nCS and nRD are de asserted These signals may be asserted and de asserted in any order Read data is v...

Page 109: ...k to back DWORD read cycles RX Data FIFO direct PIO burst reads can be performed using chip select nCS or read enable nRD An RX Data FIFO direct PIO burst read begins when both nCS and nRD are asserted Either or both of these control signals must de assert between bursts for the period specified in Table 15 11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values on page 449 The burst cycle ends ...

Page 110: ... must de assert between cycles for the period specified in Table 15 12 PIO Write Cycle Timing Values on page 450 They may be asserted and de asserted in any order Either or both of these control signals must be de asserted between cycles for the period specified The PIO write cycle is illustrated in the functional timing diagram in Figure 8 7 The END_SEL signal has the same timing characteristics ...

Page 111: ...rted in any order The TX Data FIFO direct PIO write cycle is illustrated in the functional timing diagram in Figure 8 8 Note A 9 3 are ignored during TX Data FIFO direct PIO writes Please refer to Section 15 5 9 TX Data FIFO Direct PIO Write Cycle Timing on page 451 for the AC timing specifications for TX Data FIFO direct PIO write operations 8 5 HBI Interrupts The HBI allows access to all interru...

Page 112: ...rial Management Interface bus This allows the Host MAC access to the PHY s internal registers via the Host MAC MII Access Register HMAC_MII_ACC and Host MAC MII Data Register HMAC_MII_DATA The Host MAC interfaces to the Switch Engine Port 0 via an internal MII Media Independent Interface connection allowing for incoming and outgoing Ethernet packet transfers The Host MAC can operate at either 100M...

Page 113: ... of the control frame is not affected by the current state of the Pause timer value that may be set due to a recently received control frame 9 2 2 Half Duplex Flow Control Backpressure In half duplex mode back pressure is used for flow control Whenever the receive buffer FIFO becomes full or crosses a certain threshold level the Host MAC starts sending a jam signal The Host MAC transmit logic ente...

Page 114: ...fer to the Section 14 3 1 Host MAC Control Register HMAC_CR on page 270 for more information on this register If the frame fails the filter the Host MAC does not receive the packet The host has the option of accepting or ignoring the packet Note This filtering function is performed after any switch fabric filtering functions The user must ensure the switch filtering is setup properly to allow pack...

Page 115: ..._HASHH or HMAC_HASHL while the other five bits determine the bit within the register A value of 00000 selects Bit 0 of the HMAC_HASHL register and a value of 11111 selects Bit 31 of the HMAC_HASHH register 9 4 3 Hash Perfect Filtering In hash perfect filtering if the received frame is a physical address the Host MAC packet filter will perfect filter the incoming frame s destination field with the ...

Page 116: ...hardware reset or soft reset the Host MAC loads the first value written to the HMAC_WUFF register to the first DWORD in the wake up frame filter filter 0 byte mask The second value written to this register is loaded to the second DWORD in the wake up frame filter filter 1 byte mask and so on for all eight DWORDs The wake up frame filter functionally is described below The Host MAC supports four pr...

Page 117: ...ed Filter 1 Command Reserved Filter 0 Command Filter 3 Offset Filter 2 Offset Filter 1Offset Filter 0 Offset Filter 1 CRC 16 Filter 0 CRC 16 Filter 3 CRC 16 Filter 2 CRC 16 Table 9 3 Filter i Byte Mask Bit Definitions FILTER I BYTE MASK DESCRIPTION FIELD DESCRIPTION 31 Must be zero 0 30 0 Byte Mask If bit j of the byte mask is set the CRC machine processes byte number pattern offset j of the incom...

Page 118: ...agic Packet requirements Once the address requirement has been met the Host MAC checks the received frame for the pattern 48 hFF_FF_FF_FF_FF_FF after the destination and source address field The Host MAC then looks in the frame for 16 repetitions of the Host MAC address without any breaks or interruptions In case of a break in the 16 address repetitions the Host MAC again scans for the 48 hFF_FF_F...

Page 119: ...et unicast qualification is also loaded into the Switch Fabric MAC address registers for pause packet flow control Switch Fabric MAC Address Low Register SWITCH_MAC_ADDRL and Switch Fabric MAC Address High Register SWITCH_MAC_ADDRH These two sets of registers are loaded simultaneously via the same EEPROM byte addresses Table 9 7 below illustrates the byte ordering of the HMAC_ADDRL SWITCH_MAC_ADDR...

Page 120: ... the TX or RX Data FIFOs at any of these alias port locations as they all function identically and contain the same data This alias port addressing is implemented to allow hosts to burst through sequential addresses The TX and RX Status FIFOs can each be read from two register locations the Status FIFO Port and the Status FIFO PEEK The TX and RX Status FIFO Ports 48h and 40h respectively will perf...

Page 121: ...allocation by setting the TX FIFO Size TX_FIF_SZ field in the Hardware Configuration Register HW_CFG The TX_FIF_SZ field selects the total allocation for the TX data path including the TX Status FIFO size The TX Status FIFO size is fixed at 512 Bytes 128 TX Status DWORDs The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder being the TX Data FIFO Size The minimum s...

Page 122: ...This field can be used by the LAN software driver for any application Packet Tags is only one application example The Packet Length field in the TX command specifies the number of bytes in the associated packet All Packet Length fields must have the same value for all buffers in a given packet Hardware compares the Packet Length field and the actual amount of data received by the Ethernet controll...

Page 123: ...en fully loaded into the TX FIFO contained in the LAN9312 and transmitted This feature is enabled through the TX command Interrupt on Completion field Upon completion of transmission irrespective of success or failure the status of the transmission is written to the TX Status FIFO TX status is available to the host and may be read using PIO operations An interrupt can be optionally enabled by the ...

Page 124: ... must be taken into account when calculating the actual TX Data FIFO usage Please refer to Section 9 8 5 Calculating Actual TX Data FIFO Usage for a detailed explanation on calculating the actual TX Data FIFO usage 9 8 2 TX Command Format The TX command instructs the TX FIFO controller on handling the subsequent buffer The command precedes the data to be transmitted The TX command is divided into ...

Page 125: ...ield to guarantee future compatibility 20 16 Data Start Offset bytes This field specifies the offset of the first byte of TX data The offset value can be anywhere from 0 bytes to a 31 byte offset 15 14 Reserved These bits are reserved Always write zeros to this field to guarantee future compatibility 13 First Segment FS When set this bit indicates that the associated buffer is the first segment of...

Page 126: ...ny arbitrary byte alignment The first buffer of any transmit packet can be any length Middle buffers i e those with First Segment Last Segment 0 must be greater than or equal to 4 bytes in length The final buffer of any transmit packet can be any length Table 9 11 TX Command B Format BITS DESCRIPTION 31 16 Packet Tag The host should write a unique packet identifier to this field This identifier is...

Page 127: ...7 2 MIL FIFOs on page 120 9 8 4 TX Status Format TX status is passed to the host CPU through a separate FIFO mechanism A status word is returned for each packet transmitted Data transmission is suspended if the TX Status FIFO becomes full Data transmission will resume when the host reads the TX status and there is room in the FIFO for more TX Status data The host can optionally choose to not read ...

Page 128: ...ed into three buffers The three buffers are as follows Buffer 0 7 Byte Data Start Offset 79 Bytes of payload data 16 Byte Buffer End Alignment Buffer 1 0 Byte Data Start Offset 15 Bytes of payload data 16 Byte Buffer End Alignment Buffer 2 10 Byte Data Start Offset 17 Bytes of payload data 9 Late Collision When set indicates that the packet transmission was aborted after the collision window of 64...

Page 129: ...cket Length 111 TX Command A 0 31 TX Command B 10 Byte End Offset Padding 15 Byte Payload Buffer End Alignment 1 Data Start Offset 0 First Segment 0 Last Segment 0 Buffer Size 15 Packet Length 111 TX Command A 0 31 TX Command B Buffer End Alignment 1 Data Start Offset 10 First Segment 0 Last Segment 1 Buffer Size 17 Packet Length 111 10 Byte Data Start Offset TX Command A TX Command B TX Command A...

Page 130: ...for this example and also shows how data is passed to the TX Data FIFO Note that the packet resides in a single TX Buffer therefore both the FS and LS bits are set in TX command A Figure 9 6 TX Example 2 TX Command A 0 31 TX Command B Data Written to the Memory Mapped TX Data FIFO Port TX Command B 183 Byte Payload Data Data Start Offset 6 First Segment 1 Last Segment 1 Buffer Size 183 Packet Leng...

Page 131: ...rnet controller will assert the Transmitter Error TXE flag Host overrun of the TX Data FIFO Overrun of the TX Status FIFO unless TXSAO is enabled 9 8 8 Stopping and Starting the Transmitter To halt the transmitter the host must set the STOP_TX bit in the Transmit Configuration Register TX_CFG The transmitter will finish sending the current frame if there is a frame transmission in progress When th...

Page 132: ...the event that the end of the packet does not align with the host burst boundary This feature is necessary when the LAN9312 is operating in a system that always performs multi DWORD bursts In such cases the LAN9312 must guarantee that it can transfer data in multiples of the Burst length regardless of the actual packet length When configured to do so the LAN9312 will add extra data at the end of t...

Page 133: ... Revision 1 4 08 19 08 DATASHEET Figure 9 7 Host Receive Routine Using Interrupts Figure 9 8 Host Receive Routine Using Polling Not Last Packet Idle Read RX Status DWORD init Read RX Packet Last Packet RX Interrupt Not Last Packet Read RX_FIFO_INF Read RX Status DWORD init Read RX Packet Last Packet Valid Status DWORD ...

Page 134: ...st forward the RX Data FIFO not the RX Status FIFO After an RX fast forward operation the RX status must still be read from the RX Status FIFO The receiver does not have to be stopped to perform a fast forward operation 9 9 1 2 Force Receiver Discard Receiver Dump In addition to the Receive data Fast Forward feature LAN9312 also implements a receiver dump feature This feature allows the host proce...

Page 135: ...rror Status ES When set this bit indicates that the Host MAC Interface Layer MIL has reported an error This bit is the Internal logical or of bits 11 7 6 and 1 14 Reserved These bits are reserved Reads 0 13 Broadcast Frame When set this bit indicates that the received frame has a Broadcast address 12 Length Error LE When set this bit indicates that the actual length does not match with the length ...

Page 136: ...cates that the frame has seen a collision after the collision window This indicates that a late collision has occurred 5 Frame Type When set this bit indicates that the frame is an Ethernet type frame Length Type field in the frame is greater than 1500 When reset it indicates the incoming frame was an 802 3 type frame This bit is not set for Runt frames less than 14 bytes 4 Receive Watchdog time o...

Page 137: ...I2C Microwire Master EEPROM Controller Based on the configuration strap eeprom_type_strap the I2 C Microwire EEPROM controller supports either Microwire or I2 C compatible EEPROMs The I2 C Microwire serial management pins functionality and characteristics differ dependant on the selected EEPROM type as summarized in Table 10 1 Note When the EEPROM Loader is running it has exclusive use of the I2C ...

Page 138: ... value If the operation is a WRITE the EPC_ADDRESS field in the EEPROM Command Register E2P_CMD must also be set to the desired location The command is executed when the EPC_BUSY bit of the EEPROM Command Register E2P_CMD is set The completion of the operation is indicated when the EPC_BUSY bit is cleared When issuing a READ command the EPC_COMMAND and EPC_ADDRESS fields of the EEPROM Command Regi...

Page 139: ...me is also expired the clock will rise and the cycle will continue In the event that the slave device holds the clock low for more than 30mS the current command sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register E2P_CMD is set Both the clock and data signals have Schmitt trigger inputs and digital input filters The digital filters reject pulses that are less than 100nS Note...

Page 140: ...A line while EE_SCL is high The bus is considered to be busy following a start condition and is considered free 4 7uS 1 3uS for 100KHz and 400KHz operation respectively following a stop condition The bus stays busy following a repeated start condition instead of a stop condition Starts and repeated starts are otherwise functionally equivalent Data Valid Data is valid following the start condition ...

Page 141: ...trol code is 1010b For single byte addressing EEPROMs the chip block select bits are used for address bits 10 9 and 8 For double byte addressing EEPROMs the chip block select bits are set low The direction bit is set low to indicate the address is being written Figure 10 3 illustrates typical I2 C EEPROM addressing bit order for single and double byte addressing Figure 10 2 I2C Cycle Figure 10 3 I...

Page 142: ... acknowledge followed by 8 bits of data If the EEPROM slave fails to send an acknowledge then the sequence is aborted and the EPC_TIMEOUT bit in the EEPROM Command Register E2P_CMD is set The I2C master then sends an acknowledge and the EEPROM responds with the next 8 bits of data This continues until the last desired byte is read at which point the I2 C master sends a no acknowledge followed by a...

Page 143: ...e EEPROM to determine when the byte write is finished A start condition is sent followed by a control byte with a control code of 1010b chip block select bits low and the R W bit low If the EEPROM is finished with the byte write it will respond with an acknowledge Otherwise it will respond with a no acknowledge and the I2C master will repeat the poll If the acknowledge does not occur within 30mS a...

Page 144: ... 10 6 detail the Microwire command set including the number of clock cycles required for 7 9 and 11 address bits respectively These commands are detailed in the following sections as well as in Section 14 2 4 1 EEPROM Command Register E2P_CMD on page 197 Table 10 3 Microwire EEPROM Size Ranges eeprom_size_strap 1 0 OF ADDRESS BITS EEPROM SIZE EEPROM TYPES 00 7 128 x 8 93xx46A 01 9 256 x 8 and 512 ...

Page 145: ...A6 A5 A4 A3 A2 A1 A0 D7 D0 RDY BSY 20 WRAL 1 00 0 1 X X X X X X X D7 D0 RDY BSY 20 Table 10 6 Microwire Command Set for 11 Address Bits INST START BIT OPCODE ADDRESS DATA TO EEPROM DATA FROM EEPROM OF CLOCKS ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RDY BSY 14 ERAL 1 00 1 0 X X X X X X X X X RDY BSY 14 EWDS 1 00 0 0 X X X X X X X X X Hi Z 14 EWEN 1 00 1 1 X X X X X X X X X Hi Z 14 READ 1 10 A10...

Page 146: ...tiate a bulk erase of the entire EEPROM The EPC_TIMEOUT bit of the EEPROM Command Register E2P_CMD is set if the EEPROM does not respond within 30mS 10 2 3 4 EWDS Erase Write Disable After this command is issued the EEPROM will ignore erase and write commands To re enable erase write operations the EWEN command must be issued Figure 10 8 EEPROM ERAL Cycle Figure 10 9 EEPROM EWDS Cycle 0 1 0 1 0 EE...

Page 147: ...nt or until power is cycled Note The EEPROM will power up in the erase write disabled state Any erase or write operations will fail until an EWEN command is issued 10 2 3 6 READ Read Location This command will cause a read of the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register E2P_CMD The result of the read is available in the EEPROM Data Register E2P_DATA Figure...

Page 148: ...e EEPROM Command Register E2P_CMD The EPC_TIMEOUT bit of the EEPROM Command Register E2P_CMD is set if the EEPROM does not respond within 30mS 10 2 3 8 WRAL Write All If erase write operations are enabled in the EEPROM this command will cause the contents of the EEPROM Data Register E2P_DATA to be written to every EEPROM memory location The EPC_TIMEOUT bit of the EEPROM Command Register E2P_CMD is...

Page 149: ...ach section of EEPROM contents is discussed in detail in the following sections 10 2 4 1 EEPROM Loader Operation Upon a pin reset nRST power on reset POR digital reset DIGITAL_RST bit in the Reset Control Register RESET_CTL or upon the issuance of a RELOAD command via the EEPROM Command Register E2P_CMD the EPC_BUSY bit in the EEPROM Command Register E2P_CMD will be set While the EEPROM Loader is ...

Page 150: ...ost MAC and switch MAC Address Registers Read Byte 7 11 Byte 7 A5h Y Write Bytes 8 11 into Configuration Strap registers Update PHY registers Update VPHY registers Update LED_CFG MANUAL_FC_1 MANUAL_FC_2 and MANUAL_FC_mii registers Read Byte 12 Byte 12 A5h Perform register data load loop Soft Reset Byte 0 A5h Read Bytes 1 6 Write Bytes 1 6 into Host MAC Address Registers Y Y EPC_BUSY 1 Read Byte 0 ...

Page 151: ...ow Register HMAC_ADDRL During this time the EPC_BUSY bit in the EEPROM Command Register E2P_CMD is set Note The switch MAC address registers are not reloaded due to this condition 10 2 4 4 Soft Straps The 7th byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag If this byte has a value of A5h the next 4 bytes of data 8 11 are written into the configuration strap reg...

Page 152: ...n with the new defaults as detailed in Section 14 2 8 8 Virtual PHY Special Control Status Register VPHY_SPECIAL_CONTROL_STATUS on page 257 The Virtual PHY Basic Control Register VPHY_BASIC_CTRL is written with the new defaults as detailed in Section 14 2 8 1 Virtual PHY Basic Control Register VPHY_BASIC_CTRL on page 246 Additionally the Restart Auto negotiation bit is set in this register This re...

Page 153: ...ce Access Register PMI_ACCESS are cleared before performing any register write The EEPROM Loader checks that the EEPROM address space is not exceeded If so it will stop and set the EEPROM Loader Address Overflow bit in the EEPROM Command Register E2P_CMD The address limit is based on the eeprom_size_strap which specifies a range of sizes The address limit is set to the largest value of the specifi...

Page 154: ... by master and slave clock devices to pass time information in order to achieve clock synchronization Five network message types are defined Sync Delay_Req Follow_Up Delay_Resp Management Only the first four message types Sync Delay_Req Follow_Up Delay_Resp are used for clock synchronization Using these messages the protocol software may calculate the offset and network delay between time stamps a...

Page 155: ...n and time stamp related GPIO event generation Figure 11 1 IEEE 1588 Block Diagram 10 100 PHY Ethernet 10 100 PHY MII Ethernet IEEE 1588 Time Stamp MII To Host MAC IEEE 1588 Time Stamp IEEE 1588 Time Stamp Sync Delay_Req Msg Detect RX Sync Delay_Req Msg Detect TX Clock Capture RX Src UUID Capture RX Sequence ID Capture RX IRQ Flag Clock Capture TX Src UUID Capture TX Sequence ID Capture TX IRQ Fla...

Page 156: ...s defined as data from the PHY from the outside world and transmit is defined as data to the PHY This is consistent with the point of view of where the partner clock resides LAN9312 receives packets from the partner via the PHY etc For the time stamp module connected to the Host MAC Port 0 the definition of transmit and receive is reversed Receive is defined as data from the switch fabric while tr...

Page 157: ...Sequence ID Source UUID High WORD Transmit Capture Register 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x and Port x 1588 Source UUID Low DWORD Transmit Capture Register 1588_SRC_UUID_LO_TX_CAPTURE_x The corresponding maskable interrupt flag is set in the 1588 Interrupt Status and Enable Register 1588_INT_STS_EN Refer to Section 11 6 IEEE 1588 Interrupts on page 160 for information on IEEE 1588 interrupts ...

Page 158: ...ddress it is further qualified as a Sync or Delay_Req message type On Ethernet PTP uses UDP messages Within the UDP payload is the PTP control byte offset 32 starting at 0 This byte determines the message type 0x00 for a Sync message 0x01 for a Delay_Req message The UDP payload starts at packet byte offset 42 from 0 for untagged packets and at byte offset 46 for tagged packets Note Both tagged and...

Page 159: ...disrupt linear time If the clock must be adjusted during operation of the 1588 protocol it is preferred to adjust the Addend value effectively speeding up or slowing down the clock until the correct time is achieved The 64 bit IEEE 1588 clock consists of the 32 bit 1588 Clock Addend Register 1588_CLOCK_ADDEND that is added to a 32 bit Accumulator every 100 MHz clock Upon overflow of the Accumulato...

Page 160: ...Target and Reload Add Registers are 64 bits they require two 32 bit write cycles one to each half before the registers are affected The writes may be in any order 11 5 IEEE 1588 GPIOs In addition to time stamping PTP packets the IEEE 1588 clock value can be saved into a set of clock capture registers based on the GPIO 9 8 inputs When configured as outputs GPIO 9 8 can be used to output a signal ba...

Page 161: ...PT_LOAD field at any time e g before or after the TIMER_EN bit is asserted Once enabled the GPT counts down until it reaches 0000h or until a new pre load value is written to the GPT_LOAD field At 0000h the counter wraps around to FFFFh asserts the GPT interrupt status bit GPT_INT in the Interrupt Status Register INT_STS asserts the IRQ interrupt if GPT_INT_EN is set in the Interrupt Status Regist...

Page 162: ...Interrupt Status and Enable Register GPIO_INT_STS_EN All GPIO interrupts are configured to low logic level triggering GPIO_INT_POL 11 0 cleared in General Purpose I O Configuration Register GPIO_CFG Note GPIO 7 0 may be configured as LED outputs by default dependant on the LED_en_stap 7 0 configuration straps Refer to Section 13 3 LED Operation for additional information The direction and buffer t...

Page 163: ...mpare events occur when the value loaded into the 1588 Clock Target High DWORD Register 1588_CLOCK_TARGET_HI and 1588 Clock Target Low DWORD Register 1588_CLOCK_TARGET_LO matches the current IEEE 1588 clock value in the 1588 Clock High DWORD Register 1588_CLOCK_HI and 1588 Clock Low DWORD Register 1588_CLOCK_LO Upon detection of a clock target compare event GPIO 9 8 can be configured to output a 1...

Page 164: ...ins are configured as LED outputs by setting the corresponding LED_EN bit in the LED Configuration Register LED_CFG When configured as a LED the pin is an open drain active low output and the GPIO related input buffer and pull up are disabled The LED outputs are always active low As a result a low signal on the LED pin equates to the LED on and a high signal equates to the LED off The functions as...

Page 165: ... will be held high if the port does not have a valid link 100Link Activity A steady low output indicates the port has a valid link and the speed is 100Mbps The signal is pulsed high for 80mS to indicate TX or RX activity on the port The signal is then driven low for a minimum of 80mS after which the process will repeat if RX or TX activity is again detected The signal will be held high if the port...

Page 166: ...sters on page 307 Figure 14 1 contains an overall base register memory map of the LAN9312 This memory map is not drawn to scale and should be used for general reference only Note Register bit type definitions are provided in Section 1 3 Register Nomenclature on page 19 Note Not all LAN9312 registers are memory mapped or directly addressable For details on the accessibility of the various LAN9312 r...

Page 167: ...s port locations as they all function identically and contain the same data This alias port addressing is implemented to allow hosts to burst through sequential addresses 14 1 2 TX RX Status FIFO s The TX and RX Status FIFO s can each be read from two register locations the Status FIFO Port and the Status FIFO PEEK The TX and RX Status FIFO Ports 048h and 040h respectively will perform a destructi...

Page 168: ...ge 243 Section 14 2 8 Virtual PHY on page 245 Section 14 2 9 Miscellaneous on page 259 Table 14 1 System Control and Status Registers ADDRESS OFFSET SYMBOL REGISTER NAME 050h ID_REV Chip ID and Revision Register Section 14 2 9 1 054h IRQ_CFG Interrupt Configuration Register Section 14 2 1 1 058h INT_STS Interrupt Status Register Section 14 2 1 2 05Ch INT_EN Interrupt Enable Register Section 14 2 1...

Page 169: ... Source UUID Low DWORD Receive Capture Register Section 14 2 5 4 110h 1588_CLOCK_HI_TX_CAPTURE_1 Port 1 1588 Clock High DWORD Transmit Capture Register Section 14 2 5 5 114h 1588_CLOCK_LO_TX_CAPTURE_1 Port 1 1588 Clock Low DWORD Transmit Capture Register Section 14 2 5 6 118h 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 Port 1 1588 Sequence ID Source UUID High WORD Transmit Capture Register Section 14 2 5...

Page 170: ..._HI_CAPTURE_GPIO_8 GPIO 8 1588 Clock High DWORD Capture Register Section 14 2 5 9 164h 1588_CLOCK_LO_CAPTURE_GPIO_8 GPIO 8 1588 Clock Low DWORD Capture Register Section 14 2 5 10 168h 1588_CLOCK_HI_CAPTURE_GPIO_9 GPIO 9 1588 Clock High DWORD Capture Register Section 14 2 5 11 16Ch 1588_CLOCK_LO_CAPTURE_GPIO_9 GPIO 9 1588 Clock Low DWORD Capture Register Section 14 2 5 12 170h 1588_CLOCK_HI 1588 Cl...

Page 171: ...ter Section 14 2 8 4 1D0h VPHY_AN_ADV Virtual PHY Auto Negotiation Advertisement Register Section 14 2 8 5 1D4h VPHY_AN_LP_BASE_ABILITY Virtual PHY Auto Negotiation Link Partner Base Page Ability Register Section 14 2 8 6 1D8h VPHY_AN_EXP Virtual PHY Auto Negotiation Expansion Register Section 14 2 8 7 1DCh VPHY_SPECIAL_CONTROL_STATUS Virtual PHY Special Control Status Register Section 14 2 8 8 1E...

Page 172: ...ear INT_DEAS_CLR Writing a 1 to this register clears the de assertion counter in the Interrupt Controller thus causing a new de assertion interval to begin regardless of whether or not the Interrupt Controller is currently in an active de assertion interval 0 Normal operation 1 Clear de assertion counter R W SC 0h 13 Interrupt De assertion Status INT_DEAS_STS When set this bit indicates that inter...

Page 173: ...en set the IRQ output is active high When the IRQ is configured as an open drain output via the IRQ_TYPE bit this bit is ignored and the interrupt is always active low 0 IRQ active low output 1 IRQ active high output R W NASR Note 14 1 0b 3 1 RESERVED RO 0 IRQ Buffer Type IRQ_TYPE When this bit is cleared the IRQ pin functions as an open drain output for use in a wired or interrupt configuration W...

Page 174: ...errupt Event SWITCH_INT This bit indicates an interrupt event from the Switch Fabric This bit should be used in conjunction with the Switch Global Interrupt Pending Register SW_IPR to determine the source of the interrupt event within the Switch Fabric RO 0b 27 Port 2 PHY Interrupt Event PHY_INT2 This bit indicates an interrupt event from the Port 2 PHY The source of the interrupt can be determine...

Page 175: ...ceiver has encountered an error Please refer to Section 9 9 5 Receiver Errors on page 136 for a description of the conditions that will cause an RXE R WC 0b 13 Transmitter Error TXE When generated indicates that the Host MAC transmitter has encountered an error Please refer to Section 9 8 7 Transmitter Errors on page 131 for a description of the conditions that will cause a TXE R WC 0b 12 GPIO Int...

Page 176: ...4 RX Status FIFO Full Interrupt RSFF This interrupt is generated when the RX Status FIFO is full R WC 0b 3 RX Status FIFO Level Interrupt RSFL This interrupt is generated when the RX Status FIFO reaches the programmed level in the RX Status Level field of the FIFO Level Interrupt Register FIFO_INT R WC 0b 2 0 RESERVED RO BITS DESCRIPTION TYPE DEFAULT ...

Page 177: ...7 Port 2 PHY Interrupt Event Enable PHY_INT2_EN R W 0b 26 Port 1 PHY Interrupt Event Enable PHY_INT1_EN R W 0b 25 TX Stopped Interrupt Enable TXSTOP_INT_EN R W 0b 24 RX Stopped Interrupt Enable RXSTOP_INT_EN R W 0b 23 RX Dropped Frame Counter Halfway Interrupt Enable RXDFH_INT_EN R W 0b 22 RESERVED RO 21 TX IOC Interrupt Enable TIOC_INT_EN R W 0b 20 RX DMA Interrupt Enable RXD_INT_EN R W 0b 19 GP ...

Page 178: ...ace Datasheet Revision 1 4 08 19 08 178 SMSC LAN9312 DATASHEET 5 RESERVED This bit must be written with 0b for proper operation R W 0b 4 RX Status FIFO Full Interrupt Enable RSFF_EN R W 0b 3 RX Status FIFO Level Interrupt Enable RSFL_EN R W 0b 2 0 RESERVED RO BITS DESCRIPTION TYPE DEFAULT ...

Page 179: ...a FIFO Available Interrupt TDFA will be generated in the Interrupt Status Register INT_STS R W 48h 23 16 TX Status Level The value in this field sets the level in number of DWORD s at which the TX Status FIFO Level Interrupt TSFL will be generated When the TX Status FIFO used space is greater than this value a TX Status FIFO Level Interrupt TSFL will be generated in the Interrupt Status Register I...

Page 180: ... be maintained on the last data transfer of a buffer The LAN9312 will add extra DWORD s of data up to the alignment specified in the table below The host is responsible for removing these extra DWORD s This mechanism can be used to maintain cache line alignment on host processors Note The desired RX End Alignment must be set before reading a packet The RX End Alignment can be changed between readi...

Page 181: ... valid data will be shifted by the number of bytes specified in this field An offset of 0 31 bytes is a valid number of offset bytes Note The two LSBs of this field D 9 8 must not be modified while the RX is running The receiver must be halted and all data purged before these two bits can be modified The upper three bits DWORD offset may be modified while the receiver is running Modifications to t...

Page 182: ...rs are cleared to zero WO SC 0b 13 3 RESERVED RO 2 TX Status Allow Overrun TXSAO When this bit is cleared Host MAC data transmission is suspended if the TX Status FIFO becomes full Setting this bit high allows the transmitter to continue operation with a full TX Status FIFO Note This bit does not affect the operation of the TX Status FIFO Full Interrupt TSFF R W 0b 1 Transmitter Enable TX_ON When ...

Page 183: ... BITS DESCRIPTION TYPE DEFAULT 31 RX Data FIFO Fast Forward RX_FFWD Writing a 1 to this bit causes the RX Data FIFO to fast forward to the start of the next frame This bit will remain high until the RX Data FIFO fast forward operation has completed No reads should be issued to the RX Data FIFO while this bit is high Note Please refer to section Section 9 9 1 1 Receive Data FIFO Fast Forward on pag...

Page 184: ...s BITS DESCRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 16 RX Status FIFO Used Space RXSUSED This field indicates the amount of space in DWORD s currently used in the RX Status FIFO RO 0b 15 0 RX Data FIFO Used Space RXDUSED This field indicates the amount of space in bytes used in the RX Data FIFO For each receive frame the field is incremented by the length of the receive data In cases where the pa...

Page 185: ...ta FIFO and the used space in the TX Status FIFO Offset 080h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 16 TX Status FIFO Used Space TXSUSED This field indicates the amount of space in DWORD s currently used in the TX Status FIFO RO 0b 15 0 TX Data FIFO Free Space TXFREE This field indicates the amount of space in bytes available in the TX Data FIFO The application should neve...

Page 186: ...eceive frames that have been dropped by the Host MAC Offset 0A0h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 RX Dropped Frame Counter RX_DFC This counter is incremented every time a receive frame is dropped by the Host MAC RX_DFC is cleared on any read of this register Note The interrupt RXDFH_INT bit 23 of the Interrupt Status Register INT_STS can be issued when this counter passes through it...

Page 187: ...IPTION TYPE DEFAULT 31 CSR Busy When a 1 is written into this bit the read or write operation is performed to the specified Host MAC CSR This bit will remain set until the operation is complete In the case of a read this indicates that the host can read valid data from the Host MAC CSR Interface Data Register MAC_CSR_DATA Note The MAC_CSR_CMD and MAC_CSR_DATA registers must not be modified until t...

Page 188: ...ge 269 For more information on the Host MAC refer to Chapter 9 Host MAC on page 112 Offset 0A8h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Host MAC CSR Data This field contains the value read from or written to the Host MAC CSR as specified in the Host MAC CSR Interface Command Register MAC_CSR_CMD Upon a read the value returned depends on the R nW bit in the MAC_CSR_CMD register If R nW is a...

Page 189: ...s reached The pause time transmitted in this frame is programmed in the FCPT field of the Host MAC Flow Control Register HMAC_FLOW in the Host MAC CSR space During half duplex operation each incoming frame that matches the criteria in bits 3 0 of this register will be jammed for the period set in the BACK_DUR field Note This level is also used for hard wired flow control when HW_FC_EN is set in th...

Page 190: ... 0 Flow Control on Address Decode Disabled 1 Flow Control on Address Decode Enabled R W 0b 0 Flow Control on Any Frame FCANY When this bit is set the Host MAC will assert back pressure or transmit a pause frame when the AFC level is reached and any frame is received Setting this bit enables full duplex flow control when the Host MAC is operating in full duplex mode When this mode is enabled during...

Page 191: ... Interface Datasheet SMSC LAN9312 191 Revision 1 4 08 19 08 DATASHEET 8h 250uS 252 2uS 9h 300uS 302 2uS Ah 350uS 352 2uS Bh 400uS 402 2uS Ch 450uS 452 2uS Dh 500uS 502 2uS Eh 550uS 552 2uS Fh 600uS 602 2uS Table 14 2 Backpressure Duration Bit Mapping continued BACKPRESSURE DURATION ...

Page 192: ...7 16 GPIO Interrupt Polarity 11 0 GPIO_INT_POL 11 0 These bits set the interrupt polarity of the 12 GPIO pins The configured level high low will set the corresponding GPIO_INT bit in the General Purpose I O Interrupt Status and Enable Register GPIO_INT_STS_EN 0 Sets low logic level trigger on corresponding GPIO pin 1 Sets high logic level trigger on corresponding GPIO pin GPIO_INT_POL 9 8 also det...

Page 193: ...f the 12 GPIO pins 0 Corresponding GPIO pin configured as an open drain driver 1 Corresponding GPIO pin configured as a push pull driver As an open drain driver the output pin is driven low when the corresponding data register is cleared and is not driven when the corresponding data register is set As an open drain driver used for 1588 Clock Events the corresponding GPIO_EVENT_POL_8 and GPIO_EVENT...

Page 194: ...nfigured as an input 1 GPIO pin is configured as an output R W 0h 15 12 RESERVED RO 11 0 GPIO Data 11 0 GPIOD 11 0 When a GPIO pin is enabled as an output the value written to this field is output on the corresponding GPIO pin Upon a read the value returned depends on the current direction of the pin If the pin is an input the data reflects the current state of the corresponding GPIO pin If the pi...

Page 195: ...egister Bit 12 GPIO_EN of the Interrupt Enable Register INT_EN must also be set in order for an actual system level interrupt to occur Refer to Chapter 5 System Interrupts on page 49 for additional information Offset 1E8h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 28 RESERVED RO 27 16 GPIO Interrupt Enable 11 0 GPIO 11 0 _INT_EN When set these bits enable the corresponding GPIO interrupt Note T...

Page 196: ...d by the configuration strap LED_en_strap 7 0 Configuration strap values are latched on power on reset or nRST de assertion Some configuration straps can be overridden by values from the EEPROM Loader Refer to Section 4 2 4 Configuration Straps on page 40 for more information Offset 1BCh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 10 RESERVED RO 9 8 LED Function 1 0 LED_FUN 1 0 These bits contro...

Page 197: ...his bit the operation specified in the EPC_COMMAND field of this register is performed at the specified EEPROM address This bit will remain set until the selected operation is complete In the case of a read this indicates that the Host can read valid data from the EEPROM Data Register E2P_DATA The E2P_CMD and E2P_DATA registers should not be modified until this bit is cleared In the case where a w...

Page 198: ...e or write operations will fail until an EWEN command is issued WRITE Write Location If erase write operations are enabled in the EEPROM this command will cause the contents of the EEPROM Data Register E2P_DATA to be written to the EEPROM location selected by the EPC_ADDRESS field For Microwire erase write operations must be enabled in the EEPROM WRAL Write All Microwire mode only If erase write o...

Page 199: ...supported EPC_COMMAND is attempted This bit is cleared when written high Note When in Microwire mode if an EEPROM device is not connected an internal pull down on the EEDI pin will keep the EEDI signal low and allow timeouts to occur If EEDI is pulled high externally EPC commands will not time out if an EEPROM device is not connected In this case the EPC_BUSY bit will be cleared as soon as the com...

Page 200: ... 4 2 EEPROM Data Register E2P_DATA This read write register is used in conjunction with the EEPROM Command Register E2P_CMD to perform read and write operations with the serial EEPROM Offset 1B8h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 8 RESERVED RO 7 0 EEPROM Data EEPROM_DATA This field contains the data read from or written to the EEPROM R W 00h ...

Page 201: ...list of all the 1588 related registers can be seen in Table 14 1 For more information on the IEEE 1588 refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 14 2 5 1 Port x 1588 Clock High DWORD Receive Capture Register 1588_CLOCK_HI_RX_CAPTURE_x Note The selection between Sync or Delay_Req packets is based on the corresponding master slave bit in the 1588 Configuration Register 1588_...

Page 202: ...bit in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 104h Size 32 bits Port 2 124h Port 0 144h BITS DESCRIPTION TYPE DEFAULT 31 0 Time...

Page 203: ...er 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 108h Size 32 bits Port 2 128h Port 0 148h BITS DESCRIPTION TYPE DEFAULT 31 16 Sequence ID SEQ_ID This field contains ...

Page 204: ...r slave bit in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 10Ch Size 32 bits Port 2 12Ch Port 0 14Ch BITS DESCRIPTION TYPE DEFAULT 3...

Page 205: ... in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 110h Size 32 bits Port 2 130h Port 0 150h BITS DESCRIPTION TYPE DEFAULT 31 0 Timesta...

Page 206: ...t in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 114h Size 32 bits Port 2 134h Port 0 154h BITS DESCRIPTION TYPE DEFAULT 31 0 Timest...

Page 207: ...er 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 118h Size 32 bits Port 2 138h Port 0 158h BITS DESCRIPTION TYPE DEFAULT 31 16 Sequence ID SEQ_ID This field contains ...

Page 208: ... slave bit in the 1588 Configuration Register 1588_CONFIG Note There are multiple instantiations of this register one for each port of the LAN9312 Refer to Section 14 2 5 for additional information Note For Port 0 Host MAC receive is defined as data from the switch fabric while transmit is to the switch fabric Offset Port 1 11Ch Size 32 bits Port 2 13Ch Port 0 15Ch BITS DESCRIPTION TYPE DEFAULT 31...

Page 209: ... DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_8 This read only register combined with the GPIO 8 1588 Clock Low DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_8 form the 64 bit GPIO 8 timestamp capture Offset 160h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Timestamp High TS_HI This field contains the high 32 bits of the timestamp upon activation of GPIO 8 RO 00000000h ...

Page 210: ... DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_8 This read only register combined with the GPIO 8 1588 Clock High DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_8 form the 64 bit GPIO 8 timestamp capture Offset 164h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Timestamp Low TS_LO This field contains the low 32 bits of the timestamp upon activation of GPIO 8 RO 00000000h ...

Page 211: ... DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_9 This read only register combined with the GPIO 9 1588 Clock Low DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_9 form the 64 bit GPIO 9 timestamp capture Offset 168h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Timestamp High TS_HI This field contains the high 32 bits of the timestamp upon activation of GPIO 9 RO 00000000h ...

Page 212: ... DWORD Capture Register 1588_CLOCK_LO_CAPTURE_GPIO_9 This read only register combined with the GPIO 9 1588 Clock High DWORD Capture Register 1588_CLOCK_HI_CAPTURE_GPIO_9 form the 64 bit GPIO 9 timestamp capture Offset 16Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Timestamp Low TS_LO This field contains the low 32 bits of the timestamp upon activation of GPIO 9 RO 00000000h ...

Page 213: ...quency of 100MHz which can be adjusted via the 1588 Clock Addend Register 1588_CLOCK_ADDEND accordingly Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock Low DWORD Register 1588_CLOCK_LO must be written for either to be affected Note The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHO...

Page 214: ...equency of 100MHz which can be adjusted via the 1588 Clock Addend Register 1588_CLOCK_ADDEND accordingly Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock High DWORD Register 1588_CLOCK_HI must be written for either to be affected Note The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPS...

Page 215: ...nsible for adjusting the 64 bit 1588 Clock frequency Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for details on how to properly use this register Offset 178h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Clock Addend CLOCK_ADDEND This 32 bit value is added to the 1588 frequency divisor accumulator every cycle This allows the base 100MHz frequency of the 64 bit 1588 Clock t...

Page 216: ...rget value The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock Target Low DWORD Register 1588_CLOCK_TARGET_LO must be written for either to be affected Offset 17Ch Size 32 bits BITS DESCRIP...

Page 217: ...arget value The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock Target High DWORD Register 1588_CLOCK_TARGET_HI must be written for either to be affected Offset 180h Size 32 bits BITS DESCR...

Page 218: ...ed to the 1588 Clock Compare value when a clock compare event occurs and the Reload Add RELOAD_ADD bit of the 1588 Configuration Register 1588_CONFIG is set Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock Target Reload Add Low DWORD Register 1588_CLOCK_TARGET_RELOAD_LO must be written for either to be affected...

Page 219: ...urs Whether this value is reloaded or added is determined by the Reload Add RELOAD_ADD bit of the 1588 Configuration Register 1588_CONFIG Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Note Both this register and the 1588 Clock Target Reload High DWORD Register 1588_CLOCK_TARGET_RELOAD_HI must be written for either to be affected Offset 188h Size 32 b...

Page 220: ...the 48 bit Auxiliary user defined MAC address The Auxiliary MAC address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register 1588_CONFIG Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Offset 18Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 Auxiliar...

Page 221: ...I forms the 48 bit Auxiliary user defined MAC address The Auxiliary MAC address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register 1588_CONFIG Refer to Chapter 11 IEEE 1588 Hardware Time Stamp Unit on page 154 for additional information Offset 190h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Auxiliary MAC Addr...

Page 222: ...nable Port 2 MAC_ALT2_EN_2 This bit enables disables the alternate MAC address 2 on Port 2 0 Disables alternate MAC address on Port 2 1 Enables MAC address 01 00 5E 00 01 83 as a PTP address on Port 2 R W 0b 27 Alternate MAC Address 3 Enable Port 2 MAC_ALT3_EN_2 This bit enables disables the alternate MAC address 3 on Port 2 0 Disables alternate MAC address on Port 2 1 Enables MAC address 01 00 5E...

Page 223: ...Defined MAC Address Enable Port 1 MAC_USER_EN_1 This bit enables disables the auxiliary MAC address on Port 1 The auxiliary address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO registers 0 Disables auxiliary MAC address on Port 1 1 Enables auxiliary MAC address as a PTP address on Port 1 R W 0b 17 Lock Enable RX Port 1 LOCK_RX_1 This bit enables disables the RX lock This lock prevents a ...

Page 224: ...ers 0 Disables auxiliary MAC address on Port 0 1 Enables auxiliary MAC address as a PTP address on Port 0 R W 0b 9 Lock Enable RX Port 0 Host MAC LOCK_RX_MII This bit enables disables the RX lock This lock prevents a 1588 capture from overwriting the Clock UUDI and Sequence ID values if the 1588 RX interrupt for Port 0 is ready set due to a previous capture 0 Disables RX Port 0 Lock 1 Enables RX P...

Page 225: ...Mode GPIO_EVENT_8 These bits determine the output on GPIO 8 when a clock target compare event occurs 00 100ns pulse output 01 Toggle output 10 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output 11 RESERVED Note The 1588_GPIO_OE 8 bit in the General Purpose I O Configuration Register GPIO_CFG must be set in order for the GPIO output to be controlled by the 1588 block Note The polarity ...

Page 226: ...b 21 1588 Port 1 TX Interrupt Enable 1588_PORT1_TX_EN R W 0b 20 1588 Port 0 Host MAC RX Interrupt Enable 1588_MII_RX_EN R W 0b 19 1588 Port 0 Host MAC TX Interrupt Enable 1588_MII_TX_EN R W 0b 18 GPIO9 1588 Interrupt Enable 1588_GPIO9_EN R W 0b 17 GPIO8 1588 Interrupt Enable 1588_GPIO8_EN R W 0b 16 1588 Timer Interrupt Enable 1588_TIMER_EN R W 0b 15 9 RESERVED RO 8 1588 Port 2 RX Interrupt 1588_PO...

Page 227: ...S to be recognized as interrupt inputs R WC 0b 1 1588 GPIO8 Interrupt 1588_GPIO8_INT This interrupt indicates that an event on GPIO8 occurred and the 1588 clock was captured These interrupts are configured through the General Purpose I O Configuration Register GPIO_CFG register Note As 1588 capture inputs GPIO inputs are edge sensitive and must be active for greater than 40 nS to be recognized as ...

Page 228: ...current IEEE 1588 clock values from the 1588 Clock High DWORD Register 1588_CLOCK_HI and 1588 Clock Low DWORD Register 1588_CLOCK_LO Refer to section Section 11 3 IEEE 1588 Clock on page 159 for additional information Offset 19Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Clock Snapshot 1588_CLOCK_SNAPSHOT Setting this bit causes the current 1588 Clock High DWORD Register 1588_C...

Page 229: ...w control This register also provides read back of the currently enabled flow control settings whether set manually or Auto Negotiated Refer to Section 6 2 3 Flow Control Enable Logic on page 58 for additional information Note The flow control values in the PHY_AN_ADV_1 register see Section 14 4 2 5 on page 293 within the PHY are not affected by the values of this register Offset 1A0h Size 32 bits...

Page 230: ... the values this register is updated with the new values See Section 4 2 4 Configuration Straps on page 40 for more information Note 14 7 The default value of this field is determined by the manual_FC_strap_1 configuration strap The strap values are loaded during reset and can be re written by the EEPROM Loader Once the EEPROM Loader re writes the values this register is updated with the new value...

Page 231: ...itch Port 2 0 Flow control receive is currently disabled 1 Flow control receive is currently enabled RO Note 14 9 3 Port 2 Current Transmit Flow Control Enable CUR_TX_FC_2 This bit indicates the actual transmit flow setting of switch Port 2 0 Flow control transmit is currently disabled 1 Flow control transmit is currently enabled RO Note 14 9 2 Port 2 Full Duplex Receive Flow Control Enable RX_FC_...

Page 232: ...e the EEPROM Loader re writes the values this register is updated with the new values Refer to Section 6 2 3 Flow Control Enable Logic on page 58 for additional information Note 14 10 The default value of this field is determined by the FD_FC_strap_2 configuration strap The strap values are loaded during reset and can be re written by the EEPROM Loader Once the EEPROM Loader re writes the values t...

Page 233: ...must be disabled when using this feature MANUAL_FC_MII should be set TX_FC_MII RX_FC_MII and BP_EN_MII should be cleared FCANY FCADD FCBRD and FCMULT in the AFC_CFG register should be cleared R W 0b 6 Port 0 Backpressure Enable BP_EN_MII This bit enables disables the generation of half duplex backpressure on switch Port 0 0 Disable backpressure 1 Enable backpressure R W Note 14 12 5 Port 0 Current...

Page 234: ...lue this register is updated with the new values See Section 4 2 4 Configuration Straps on page 40 for more information Note 14 15 The default value of this field is determined by the manual_FC_strap_mii configuration strap The strap value is loaded during reset and can be re written by the EEPROM Loader Once the EEPROM Loader re writes the value this register is updated with the new values See Se...

Page 235: ...egisters on page 307 for details on the registers indirectly accessible via this register Offset 1ACh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Switch CSR Data CSR_DATA This field contains the value read from or written to the Switch Fabric CSR The Switch Fabric CSR is selected via the CSR Address CSR_ADDR 15 0 bits of the Switch Fabric CSR Interface Command Register SWITCH_CSR_CMD Upon a re...

Page 236: ... to the specified Switch Engine CSR 0 Write 1 Read R W 0b 29 Auto Increment AUTO_INC This bit enables disables the auto increment feature When this bit is set a write to the Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA register will automatically set the CSR Busy CSR_BUSY bit Once the write command is finished the CSR Address CSR_ADDR 15 0 will automatically increment When this bit is...

Page 237: ...register data bits 31 24 CSR_BE 2 corresponds to register data bits 23 16 CSR_BE 1 corresponds to register data bits 15 8 CSR_BE 0 corresponds to register data bits 7 0 Typically all four byte enables should be set for auto increment and auto decrement operations R W 0h 15 0 CSR Address CSR_ADDR 15 0 This field selects the 16 bit address of the Switch Fabric CSR that will be accessed with a read o...

Page 238: ...d The least significant byte of this register bits 7 0 is loaded from address 05h of the EEPROM The second byte bits 15 8 is loaded from address 06h of the EEPROM These EEPROM values are also loaded into the Host MAC Address High Register HMAC_ADDRH The Host can update the contents of this field after the initialization process has completed Refer to Section 9 6 Host MAC Address on page 119 for de...

Page 239: ...ected The least significant byte of this register bits 7 0 is loaded from address 01h of the EEPROM The most significant byte bits 31 24 is loaded from address 04h of the EEPROM These EEPROM values are also loaded into the Host MAC Address Low Register HMAC_ADDRL The Host can update the contents of this field after the initialization process has completed Refer to Section 9 6 Host MAC Address on p...

Page 240: ...Register SWITCH_CSR_CMD is mapped via Table 14 3 For more information on this method of writing to the Switch Fabric CSR s refer to Section 6 2 3 Flow Control Enable Logic on page 58 Note This set of registers is for write operations only Reads can be performed via the Switch Fabric CSR Interface Command Register SWITCH_CSR_CMD and Switch Fabric CSR Interface Data Register SWITCH_CSR_DATA register...

Page 241: ... SWE_PORT_INGRESS_CFG 1841h 25Ch SWE_ADMT_ONLY_VLAN 1842h 260h SWE_PORT_STATE 1843h 264h SWE_PRI_TO_QUE 1845h 268h SWE_PORT_MIRROR 1846h 26Ch SWE_INGRESS_PORT_TYP 1847h 270h SWE_BCST_THROT 1848h 274h SWE_ADMT_N_MEMBER 1849h 278h SWE_INGRESS_RATE_CFG 184Ah 27Ch SWE_INGRESS_RATE_CMD 184Bh 280h SWE_INGRESS_RATE_WR_DATA 184Dh 284h SWE_INGRESS_REGEN_TBL_MII 1855h 288h SWE_INGRESS_REGEN_TBL_1 1856h 28Ch...

Page 242: ...0Ah 2B0h BM_EGRSS_PORT_TYPE 1C0Ch 2B4h BM_EGRSS_RATE_00_01 1C0Dh 2B8h BM_EGRSS_RATE_02_03 1C0Eh 2BCh BM_EGRSS_RATE_10_11 1C0Fh 2C0h BM_EGRSS_RATE_12_13 1C10h 2C4h BM_EGRSS_RATE_20_21 1C11h 2C8h BM_EGRSS_RATE_22_23 1C12h 2CCh BM_VLAN_MII 1C13h 2D0h BM_VLAN_1 1C14h 2D4h BM_VLAN_2 1C15h 2D8h BM_IMR 1C20h 2DCh Table 14 3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map continued REGISTER ...

Page 243: ...Refer to Section 10 2 4 EEPROM Loader on page 149 for additional information 14 2 7 1 PHY Management Interface Data Register PMI_DATA This register is used in conjunction with the PHY Management Interface Access Register PMI_ACCESS to perform write operations to the PHYs Note This register is only accessible by the EEPROM Loader and NOT by the Host bus Refer to Section 10 2 4 EEPROM Loader on page...

Page 244: ...EEPROM Loader and NOT by the Host bus Refer to Section 10 2 4 EEPROM Loader on page 149 for additional information Offset 0A8h EEPROM Loader Access Only Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 11 PHY Address PHY_ADDR These bits select the PHY device being accessed Refer to Section 7 1 1 PHY Addressing on page 82 for information on PHY address assignments WO 00000b 10 6 MII ...

Page 245: ... Virtual PHY functionality and operation information see Section 7 3 Virtual PHY on page 96 Note All Virtual PHY registers follow the IEEE 802 3 clause 22 2 4 specified MII management register set All functionality and bit definitions comply with these standards The IEEE 802 3 specified register index in decimal is included under the LAN9312 memory mapped offset of each Virtual PHY register as a r...

Page 246: ...re not sent to the switch fabric Instead they are looped back onto the receive path 0 Loopback mode disabled normal operation 1 Loopback mode enabled R W 0b 13 Speed Select LSB VPHY_SPEED_SEL_LSB This bit is used to set the speed of the Virtual PHY when the Auto Negotiation VPHY_AN bit is disabled 0 10 Mbps 1 100 Mbps R W 0b 12 Auto Negotiation VPHY_AN This bit enables disables Auto Negotiation Wh...

Page 247: ...col the register is 16 bits wide 7 Collision Test VPHY_COL_TEST This bit enables disables the collision test mode When set the collision signal to the Host MAC is active during transmission from the Host MAC Note It is recommended that this bit be used only when in loopback mode 0 Collision test mode disabled 1 Collision test mode enabled R W 0b 6 Speed Select MSB VPHY_SPEED_SEL_MSB This bit is no...

Page 248: ...Y able to perform 100BASE X half duplex RO 1b 12 10BASE T Full Duplex This bit displays the status of 10BASE T full duplex compatibility 0 PHY not able to perform 10BASE T full duplex 1 PHY able to perform 10BASE T full duplex RO 1b 11 10BASE T Half Duplex This bit displays the status of 10BASE T half duplex compatibility 0 PHY not able to perform 10BASE T half duplex 1 PHY able to perform 10BASE ...

Page 249: ...he IEEE 802 3 specification 6 MF Preamble Suppression This bit indicates whether the Virtual PHY accepts management frames with the preamble suppressed 0 Management frames with preamble suppressed not accepted 1 Management frames with preamble suppressed accepted RO 0b 5 Auto Negotiation Complete This bit indicates the status of the Auto Negotiation process 0 Auto Negotiation process not completed...

Page 250: ...ontained in the Virtual PHY Identification LSB Register VPHY_ID_LSB Note 14 23 The reserved bits 31 16 are used to pad the register to 32 bits so that each register is on a DWORD boundary When accessed serially through the MII management protocol the register is 16 bits wide Note 14 24 IEEE allows a value of zero in each of the 32 bits of the PHY Identifier Offset Index decimal 1C8h 2 Size 32 bits...

Page 251: ...the register to 32 bits so that each register is on a DWORD boundary When accessed serially through the MII management protocol the register is 16 bits wide Note 14 26 IEEE allows a value of zero in each of the 32 bits of the PHY Identifier Offset Index decimal 1CCh 3 Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED See Note 14 25 RO 15 10 PHY ID This field contains the lower 6 bits of th...

Page 252: ...rtner RO 0b Note 14 29 12 RESERVED RO 11 Asymmetric Pause This bit determines the advertised asymmetric pause capability 0 No Asymmetric PAUSE toward link partner advertised 1 Asymmetric PAUSE toward link partner advertised R W 0b 10 Pause This bit determines the advertised symmetric pause capability 0 No Symmetric PAUSE toward link partner advertised 1 Symmetric PAUSE toward link partner advertis...

Page 253: ... 14 30 The Pause bit defaults to 1 if the manual_FC_strap_mii strap is low and 0 if the manual_FC_strap_mii strap is high Configuration strap values are latched upon the de assertion of a chip level reset as described in Section 4 2 4 Configuration Straps on page 40 Note 14 31 Virtual 100BASE T4 is not supported Note 14 32 The Virtual PHY supports only IEEE 802 3 Only a value of 00001b should be u...

Page 254: ...indicates whether the link code word has been received from the partner and is always 1 0 Link code word not yet received from partner 1 Link code word received from partner RO 1b Note 14 34 13 Remote Fault Since there is no physical link partner this bit is not used and is always returned as 0 RO 0b Note 14 34 12 RESERVED RO 11 Asymmetric Pause This bit indicates the emulated link partner PHY asy...

Page 255: ...BASE T half duplex For more information on the Virtual PHY auto negotiation see Section 7 3 1 Virtual PHY Auto Negotiation on page 96 7 100BASE X Half Duplex This bit indicates the emulated link partner PHY 100BASE X half duplex capability 0 100BASE X half duplex ability not supported 1 100BASE X half duplex ability supported RO Note 14 36 6 10BASE T Full Duplex This bit indicates the emulated lin...

Page 256: ...bility Offset Index decimal 1D8h 6 Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED See Note 14 37 RO 15 5 RESERVED RO 4 Parallel Detection Fault This bit indicates whether a Parallel Detection Fault has been detected This bit is always 0 0 A fault hasn t been detected via the Parallel Detection function 1 A fault has been detected via the Parallel Detection function RO 0b Note 14 38 3 Li...

Page 257: ...figuration Register MAC_RX_CFG_x must be set for this port Otherwise the switch fabric will ignore receive activity when transmitting in half duplex mode This mode works even if the Isolate bit of the Virtual PHY Basic Control Register VPHY_BASIC_CTRL is set R W 0b 13 8 RESERVED RO 7 Switch Collision Test MII When set the collision signal to the switch fabric Port 0 Host MAC is active during trans...

Page 258: ...eflects the Speed Select LSB VPHY_SPEED_SEL_LSB and Duplex Mode VPHY_DUPLEX bit settings of the VPHY_BASIC_CTRL register Refer to Section 7 3 1 Virtual PHY Auto Negotiation on page 96 for information on the Auto Negotiation determination process of the Virtual PHY Note 14 44 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset Control Register RESET_CTL ...

Page 259: ... functions such as the Chip ID revision byte order testing power management hardware configuration general purpose timer and free running counter 14 2 9 1 Chip ID and Revision ID_REV This read only register contains the ID and Revision fields for the LAN9312 Note 14 46 Default value is dependent on device revision Offset 050h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 Chip ID This field indi...

Page 260: ...age 99 for additional information on byte ordering Note This register can be read while the LAN9312 is in the reset or not ready states The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write to read or read to read timing Refer to Section 8 4 2 Special Restrictions on Back to Back Write Read Cycles on page 101 and Section 8 4 3 Special Restrictions on Ba...

Page 261: ...the HW_CFG PMT_CTRL BYTE_TEST and RESET_CTL registers read access to any internal resources is forbidden while the READY bit is cleared Writes to any address are invalid until this bit is set Note This bit is identical to bit 0 of the Power Management Control Register PMT_CTRL RO 0b 26 AMDIX_EN Strap State Port 2 This bit reflects the state of the auto_mdix_strap_2 strap that connects to the PHY T...

Page 262: ... The TX Data FIFO is used for both TX data and TX commands The RX Status and Data FIFOs consume the remaining space which is equal to 16KB minus TX_FIF_SIZ See section Section 9 7 3 FIFO Memory Allocation Configuration on page 121 for more information R W 5h 15 14 RESERVED RO 13 12 RESERVED This field must be written with 00b for proper operation R W 00b 11 1 RESERVED RO 0 Soft Reset SRST Writing ...

Page 263: ...al if enabled via the PME_EN bit will be asserted in accordance with the PME_IND bit upon an energy detect event from Port 2 When set the PME_INT bit in the Interrupt Status Register INT_STS will also be asserted upon an energy detect event from Port 2 regardless of the setting of the PME_EN bit Note The EDPWRDOWN bit of the Port x PHY Mode Control Status Register PHY_MODE_CONTROL_STATUS_x of the ...

Page 264: ... detection of event 1 PME driven continuously on detection of event The PME signal can be deactivated by clearing the WOL_STS bit or by clearing the appropriate enable R W 0b 2 PME Polarity PME_POL This bit controls the polarity of the PME signal When set the PME output is an active high signal When cleared it is active low Note When PME is configured as an open drain output this field is ignored ...

Page 265: ...Count Register GPT_CNT Refer to Section 12 1 General Purpose Timer on page 161 for additional information Offset 08Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 30 RESERVED RO 29 General Purpose Timer Enable TIMER_EN This bit enables the GPT When set the GPT enters the run state When cleared the GPT is halted On the 1 to 0 transition of this bit the GPT_LOAD field of this register will be prese...

Page 266: ...rent general purpose timer GPT value The register should be used in conjunction with the General Purpose Timer Configuration Register GPT_CFG to configure and monitor the GPT Refer to Section 12 1 General Purpose Timer on page 161 for additional information Offset 090h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 General Purpose Timer Current Count GPT_CNT This 16 bit field re...

Page 267: ...Section 12 2 Free Running Clock on page 161 for additional information Offset 09Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Free Running Counter FR_CNT This field reflects the current value of the free running 32 bit counter At reset the counter starts at zero and is incremented by one every 25MHz cycle When the maximum count has been reached the counter will rollover to zero and continue c...

Page 268: ...er R W SC 0b 1 Port 1 PHY Reset PHY1_RST Setting this bit resets the Port 1 PHY The internal logic automatically holds the PHY reset for a minimum of 102uS When the Port 1 PHY is released from reset this bit is automatically cleared All writes to this bit are ignored while this bit is set Note This bit is not accessible via the EEPROM Loader R W SC 0b 0 Digital Reset DIGITAL_RST Setting this bit r...

Page 269: ...TA These registers allow access to the 10 100 Ethernet PHY registers and the switch engine via Port 0 Table 14 6 Host MAC Adressable Registers INDEX SYMBOL REGISTER NAME 00h RESERVED Reserved for Future Use 01h HMAC_CR Host MAC Control Register Section 14 3 1 02h HMAC_ADDRH Host MAC Address High Register Section 14 3 2 03h HMAC_ADDRL Host MAC Address Low Register Section 14 3 3 04h HMAC_HASHH Host...

Page 270: ...ull Duplex Mode bit is set R W 0b 22 RESERVED RO 21 Loopback operation Mode LOOPBK Selects the loop back operation modes for the Host MAC This field is only valid for full duplex mode In internal loopback mode the TX frame is received by the internal MII interface and sent back to the Host MAC without being sent to the switch fabric 0 Normal Operation Loopback disabled 1 Loopback enabled Note When...

Page 271: ...en the IA addresses are perfect address filtered according to the MAC Address register Refer to Section 9 4 3 Hash Perfect Filtering on page 115 for additional information R W 0b 12 RESERVED RO 11 Disable Broadcast Frames BCAST When set disables the reception of broadcast frames When cleared forwards all broadcast frames to the application Note When wake up frame detection is enabled via the WUEN ...

Page 272: ...om the LFSR counter to a predetermined value as in the table below Thus if the value of K 10 the Host MAC will look at the BOLMT if it is 00b then use the lower ten bits of the LFSR counter for the wait countdown If the BOLMT is 10b then it will only use the value in the first four bits for the wait countdown etc Note Slot time 512 bit times See IEEE 802 3 Spec sections 4 2 3 25 and 4 4 2 1 R W 0b...

Page 273: ...The second byte bits 15 8 is loaded from address 06h of the EEPROM Section 9 6 Host MAC Address on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address Please refer to Section 10 2 I2C Microwire Master EEPROM Controller on page 137 for more information on the EEPROM Loader Offset 2h Size 32 bits BITS DESCRIPTIO...

Page 274: ...he most significant byte of this register is loaded from address 04h of the EEPROM Section 9 6 Host MAC Address on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address Please refer to Section 10 2 I2C Microwire Master EEPROM Controller on page 137 for more information on the EEPROM Loader Offset 3h Size 32 bits...

Page 275: ...the Multicast Hash Table Hi register If the corresponding bit is 1 then the multicast frame is accepted Otherwise it is rejected If the Pass All Multicast MCPAS bit of the Host MAC Control Register HMAC_CR is set then all multicast frames are accepted regardless of the multicast hash values The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast Hash ...

Page 276: ...C Multicast Hash Table Low Register HMAC_HASHL This read write register defines the lower 32 bits of the Multicast Hash Table Please refer to the Host MAC Multicast Hash Table High Register HMAC_HASHH and Section 9 4 Address Filtering for more information Offset 5h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Lower 32 bits of the 64 bit Hash Table R W 00000000h ...

Page 277: ...0 6 MII Register Index MIIRINDA These bits select the desired MII register in the PHY R W 00000b 5 2 RESERVED RO 1 MII Write MIIWnR Setting this bit tells the PHY that this will be a write operation using the Host MAC MII Data Register HMAC_MII_DATA If this bit is cleared a read operation will occur packing the data in the Host MAC MII Data Register HMAC_MII_DATA R W 0b 0 MII Busy MIIBZY This bit ...

Page 278: ...I_ACC to access the internal PHY registers This register contains either the data to be written to the PHY register specified in the HMAC_MII_ACC Register or the read data from the PHY register whose index is specified in the HMAC_MII_ACC Register Offset 7h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 MII Data This field contains the 16 bit value read from the PHY read operati...

Page 279: ... in the PAUSE TIME field in the control frame This field must be initialized before full duplex automatic flow control is enabled R W 0000h 15 3 RESERVED RO 2 Pass Control Frames FCPASS When set the Host MAC sets the packet filter bit in the receive packet status to indicate to the application that a valid pause frame has been received The application must accept or discard a received frame based ...

Page 280: ...he bit must be set During a transfer of control frame this bit continues to be set signifying that a frame transmission is in progress After the PAUSE control frame s transmission is complete the Host MAC resets the bit to 0 Backpressure Enable BkPresEn In half duplex mode this signal functions as a backpressure enable and is set high whenever backpressure is transmitted Notes When writing this re...

Page 281: ...al frame length is increased from 1518 bytes to 1522 bytes Refer to Section 9 3 Virtual Local Area Network VLAN Support on page 113 for additional information Offset 9h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 VLAN1 Tag Identifier VTI1 This field contains the VLAN Tag used to identify VLAN1 frames This field is compared with the 13th and 14th bytes of the incoming frames f...

Page 282: ...Area Network VLAN Support on page 113 for additional information Offset Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 VLAN2 Tag Identifier VTI2 This field contains the VLAN Tag used to identify VLAN2 frames This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection Note If used this register is typically set to the standard VLAN valu...

Page 283: ... 0 Wake Up Frame Filter WFF The Wake up frame filter is configured through this register using an indexing mechanism After power on reset digital reset or soft reset the Host MAC loads the first value written to this location to the first DWORD in the Wake up frame filter filter 0 byte mask The second value written to this location is loaded to the second DWORD in the wake up frame filter filter 1...

Page 284: ...ESERVED RO 9 Global Unicast Enable GUE When set the Host MAC wakes up from power saving mode on receipt of a global unicast frame This is accomplished by enabling global unicasts as a wakeup frame qualifier A global unicast frame has the MAC Address 0 bits set to 0 R W 0b 8 7 RESERVED RO 6 Remote Wake Up Frame Received WUFR The Host MAC sets this bit upon receiving a valid Remote Wake up frame R W...

Page 285: ... index numbers is also included in Table 14 4 Note When serially accessed the Virtual PHY registers are only 16 bits wide as is standard for MII management of PHY s 14 4 2 Port 1 2 PHY Registers The Port 1 and Port 2 PHY s are comparable in functionality and have an identical set of non memory mapped registers The Port 1 and Port 2 PHY registers are not memory mapped These registers are indirectly...

Page 286: ... Register Section 14 4 2 9 27 PHY_SPECIAL_CONTROL_STAT_IND_x Port x PHY Special Control Status Indication Register Section 14 4 2 10 29 PHY_INTERRUPT_SOURCE_x Port x PHY Interrupt Source Flags Register Section 14 4 2 11 30 PHY_INTERRUPT_MASK_x Port x PHY Interrupt Mask Register Section 14 4 2 12 31 PHY_SPECIAL_CONTROL_STATUS_x Port x PHY Special Control Status Register Section 14 4 2 13 Table 14 7...

Page 287: ...ive Own Transmit bit in the Port x MAC Receive Configuration Register MAC_RX_CFG_x must be set for the specified port Otherwise the switch fabric will ignore receive activity when transmitting in half duplex mode 0 Loopback mode disabled normal operation 1 Loopback mode enabled R W 0b 13 Speed Select LSB PHY_SPEED_SEL_LSB This bit is used to set the speed of the Port x PHY when the Auto Negotiatio...

Page 288: ... is determined by the logical AND of the negation of the Auto Negotiation strap autoneg_strap_1 for Port 1 PHY autoneg_strap_2 for Port 2 PHY and the duplex select strap duplex_strap_1 for Port 1 PHY duplex_strap_2 for Port 2 PHY Essentially if the Auto Negotiation strap is set the default value is 0 otherwise the default is determined by the value of the duplex select strap Refer to Section 4 2 4...

Page 289: ...it displays the status of 10BASE T full duplex compatibility 0 PHY not able to perform 10BASE T full duplex 1 PHY able to perform 10BASE T full duplex RO 1b 11 10BASE T Half Duplex This bit displays the status of 10BASE T half duplex compatibility 0 PHY not able to perform 10BASE T half duplex 1 PHY able to perform 10BASE T half duplex RO 1b 10 100BASE T2 Full Duplex This bit displays the status o...

Page 290: ...atus of the PHY s auto negotiation 0 PHY is unable to perform auto negotiation 1 PHY is able to perform auto negotiation RO 1b 2 Link Status This bit indicates the status of the link 0 Link is down 1 Link is up RO LL 0b 1 Jabber Detect This bit indicates the status of the jabber condition 0 No jabber condition detected 1 Jabber condition detected RO LH 0b 0 Extended Capability This bit indicates w...

Page 291: ...egister PHY_ID_MSB_x This read write register contains the MSB of the Organizationally Unique Identifier OUI for the Port x PHY The LSB of the PHY OUI is contained in the Port x PHY Identification LSB Register PHY_ID_LSB_x Index decimal 2 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 0 PHY ID This field is assigned to the 3rd through 18th bits of the OUI respectively OUI 00800Fh R W 0007h ...

Page 292: ...tifier OUI for the Port x PHY The MSB of the PHY OUI is contained in the Port x PHY Identification MSB Register PHY_ID_MSB_x Index decimal 3 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 10 PHY ID This field is assigned to the 19th through 24th bits of the PHY OUI respectively OUI 00800Fh R W 30h 9 4 Model Number This field contains the 6 bit manufacturer s model number of the PHY R W 0Dh 3 0 Revi...

Page 293: ...capability 0 No Asymmetric PAUSE toward link partner advertised 1 Asymmetric PAUSE toward link partner advertised R W 0b Note 14 53 10 Symmetric Pause This bit determines the advertised symmetric pause capability 0 No Symmetric PAUSE toward link partner advertised 1 Symmetric PAUSE toward link partner advertised R W Note 14 53 Note 14 54 9 RESERVED RO 8 100BASE X Full Duplex This bit determines th...

Page 294: ...e default behavior of this bit Configuration strap values are latched upon the de assertion of a chip level reset as described in Section 4 2 4 Configuration Straps on page 40 Refer to Section 4 2 4 Configuration Straps on page 40 for configuration strap definitions Note 14 56 The default value of this bit is determined by the logical OR of the Auto Negotiation strap autoneg_strap_x and the negate...

Page 295: ...ernet Switch with 32 Bit Non PCI CPU Interface Datasheet SMSC LAN9312 295 Revision 1 4 08 19 08 DATASHEET 1 1 1 Table 14 9 10BASE T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Default 10BASE T Half Duplex Bit 5 Value ...

Page 296: ...ceived from partner RO 0b 13 Remote Fault This bit indicates whether a remote fault has been detected 0 No remote fault 1 Remote fault detected RO 0b 12 RESERVED RO 11 Asymmetric Pause This bit indicates the link partner PHY asymmetric pause capability 0 No Asymmetric PAUSE toward link partner 1 Asymmetric PAUSE toward link partner RO 0b 10 Pause This bit indicates the link partner PHY symmetric p...

Page 297: ...0BASE T full duplex capability 0 10BASE T full duplex ability not supported 1 10BASE T full duplex ability supported RO 0b 5 10BASE T Half Duplex This bit indicates the link partner PHY 10BASE T half duplex capability 0 10BASE T half duplex ability not supported 1 10BASE T half duplex ability supported RO 0b 4 0 Selector Field This field identifies the type of message being sent by Auto Negotiatio...

Page 298: ...n detected via the Parallel Detection function RO LH 0b 3 Link Partner Next Page Able This bit indicates whether the link partner has next page ability 0 Link partner does not contain next page capability 1 Link partner contains next page capability RO 0b 2 Local Device Next Page Able This bit indicates whether the local device has next page ability 0 Local device does not contain next page capabi...

Page 299: ...s BITS DESCRIPTION TYPE DEFAULT 15 14 RESERVED RO 13 Energy Detect Power Down EDPWRDOWN This bit controls the Energy Detect Power Down mode 0 Energy Detect Power Down is disabled 1 Energy Detect Power Down is enabled R W 0b 12 2 RESERVED RO 1 Energy On ENERGYON This bit indicates whether energy is detected on the line It is cleared if no valid energy is detected within 256ms This bit is unaffected...

Page 300: ...atched upon the de assertion of a chip level reset as described in Section 4 2 4 Configuration Straps on page 40 Refer to Section 4 2 4 Configuration Straps on page 40 for configuration strap definitions Note 14 60 The default value of this field is determined by the phy_addr_sel_strap configuration strap Refer to Section 7 1 1 PHY Addressing on page 82 for additional information Index decimal 18 ...

Page 301: ...ertised Auto negotiation enabled CRS is active during Transmit Receive 1100 0100 101 Repeater mode Auto negotiation enabled 100BASE TX Half Duplex is advertised CRS is active during Receive 1100 0100 110 Power Down mode In this mode the PHY wake up in Power Down mode N A N A 111 All capable Auto negotiation enabled X10X 1111 Table 14 10 MODE 2 0 Definitions continued MODE 2 0 MODE DEFINITIONS AFFE...

Page 302: ...n Straps on page 40 for configuration strap definitions 0 Port x Auto MDIX determined by strap inputs 1 Port x Auto MDIX determined by bits 14 and 13 R W NASR Note 14 61 0b 14 Auto MDIX Enable AMDIXEN When bit 15 AMDIXCTRL of this register is set this bit is used in conjunction with bit 13 Auto MDIX State to control the Port x Auto MDIX functionality as shown in Table 14 11 R W NASR Note 14 61 0b ...

Page 303: ...ce Datasheet SMSC LAN9312 303 Revision 1 4 08 19 08 DATASHEET Table 14 11 Auto MDIX Enable and Auto MDIX State Bit Functionality Auto MDIX Enable Bit 14 Auto MDIX State Bit 13 MODE 0 0 Manual mode no crossover 0 1 Manual mode crossover 1 0 Auto MDIX mode 1 1 RESERVED do not use this state ...

Page 304: ...ol Status Register PHY_MODE_CONTROL_STATUS_x has been set 0 Not source of interrupt 1 ENERGYON generated RO LH 0b 6 INT6 This interrupt source bit indicates Auto Negotiation is complete 0 Not source of interrupt 1 Auto Negotiation complete RO LH 0b 5 INT5 This interrupt source bit indicates a remote fault has been detected 0 Not source of interrupt 1 Remote fault detected RO LH 0b 4 INT4 This inte...

Page 305: ...egotiation interrupt 0 Interrupt source is masked 1 Interrupt source is enabled R W 0b 5 INT5_MASK This interrupt mask bit enables masks the remote fault interrupt 0 Interrupt source is masked 1 Interrupt source is enabled R W 0b 4 INT4_MASK This interrupt mask bit enables masks the Link Down link status negated interrupt 0 Interrupt source is masked 1 Interrupt source is enabled R W 0b 3 INT3_MAS...

Page 306: ...ON TYPE DEFAULT 15 13 RESERVED RO 12 Autodone This bit indicates the status of the Auto Negotiation on the Port x PHY 0 Auto Negotiation is not completed is disabled or is not active 1 Auto Negotiation is completed RO 0b 11 5 RESERVED Write as 0000010b ignore on read R W 0000010b 4 2 Speed Indication This field indicates the current Port x PHY speed configuration RO 000b 1 0 RESERVED R W 0b STATE ...

Page 307: ...AL_FC_MII located in the system CSR address space Table 14 12 lists the Switch CSRs and their corresponding addresses in order The switch fabric registers can be categorized into the following sub sections Section 14 5 1 General Switch CSRs on page 318 Section 14 5 2 Switch Port 0 Port 1 and Port 2 CSRs on page 322 Section 14 5 3 Switch Engine CSRs on page 366 Section 14 5 4 Buffer Manager CSRs on...

Page 308: ...AC_RX_JABB_CNT_MII Port 0 MAC Receive Jabber Error Count Register Section 14 5 2 17 041Fh MAC_RX_ALIGN_CNT_MII Port 0 MAC Receive Alignment Error Count Register Section 14 5 2 18 0420h MAC_RX_PKTLEN_CNT_MII Port 0 MAC Receive Packet Length Count Register Section 14 5 2 19 0421h MAC_RX_GOODPKTLEN_CNT_MII Port 0 MAC Receive Good Packet Length Count Register Section 14 5 2 20 0422h MAC_RX_SYMBL_CNT_M...

Page 309: ...egister Section 14 5 2 37 045Fh MAC_TX_LATECOL_MII Port 0 MAC Transmit Late Collision Count Register Section 14 5 2 38 0460h MAC_TX_EXCOL_CNT_MII Port 0 MAC Transmit Excessive Collision Count Register Section 14 5 2 39 0461h MAC_TX_SNGLECOL_CNT_MII Port 0 MAC Transmit Single Collision Count Register Section 14 5 2 40 0462h MAC_TX_MULTICOL_CNT_MII Port 0 MAC Transmit Multiple Collision Count Regist...

Page 310: ...t Count Register Section 14 5 2 14 081Ch MAC_RX_PAUSE_CNT_1 Port 1 MAC Receive Pause Frame Count Register Section 14 5 2 15 081Dh MAC_RX_FRAG_CNT_1 Port 1 MAC Receive Fragment Error Count Register Section 14 5 2 16 081Eh MAC_RX_JABB_CNT_1 Port 1 MAC Receive Jabber Error Count Register Section 14 5 2 17 081Fh MAC_RX_ALIGN_CNT_1 Port 1 MAC Receive Alignment Error Count Register Section 14 5 2 18 082...

Page 311: ...ansmit Packet Length Count Register Section 14 5 2 35 085Dh MAC_TX_BRDCST_CNT_1 Port 1 MAC Transmit Broadcast Count Register Section 14 5 2 36 085Eh MAC_TX_MULCST_CNT_1 Port 1 MAC Transmit Multicast Count Register Section 14 5 2 37 085Fh MAC_TX_LATECOL_1 Port 1 MAC Transmit Late Collision Count Register Section 14 5 2 38 0860h MAC_TX_EXCOL_CNT_1 Port 1 MAC Transmit Excessive Collision Count Regist...

Page 312: ...4 5 2 12 0C1Ah MAC_RX_MULCST_CNT_2 Port 2 MAC Receive Multicast Count Register Section 14 5 2 13 0C1Bh MAC_RX_BRDCST_CNT_2 Port 2 MAC Receive Broadcast Count Register Section 14 5 2 14 0C1Ch MAC_RX_PAUSE_CNT_2 Port 2 MAC Receive Pause Frame Count Register Section 14 5 2 15 0C1Dh MAC_RX_FRAG_CNT_2 Port 2 MAC Receive Fragment Error Count Register Section 14 5 2 16 0C1Eh MAC_RX_JABB_CNT_2 Port 2 MAC ...

Page 313: ...33 0C5Ah MAC_TX_UNDSZE_CNT_2 Port 2 MAC Transmit Undersize Count Register Section 14 5 2 34 0C5Bh RESERVED Reserved for Future Use 0C5Ch MAC_TX_PKTLEN_CNT_2 Port 2 MAC Transmit Packet Length Count Register Section 14 5 2 35 0C5Dh MAC_TX_BRDCST_CNT_2 Port 2 MAC Transmit Broadcast Count Register Section 14 5 2 36 0C5Eh MAC_TX_MULCST_CNT_2 Port 2 MAC Transmit Multicast Count Register Section 14 5 2 3...

Page 314: ... Engine VLAN Read Data Register Section 14 5 3 10 180Fh RESERVED Reserved for Future Use 1810h SWE_VLAN_CMD_STS Switch Engine VLAN Command Status Register Section 14 5 3 11 1811h SWE_DIFFSERV_TBL_CMD Switch Engine DIFSERV Table Command Register Section 14 5 3 12 1812h SWE_DIFFSERV_TBL_WR_DATA Switch Engine DIFFSERV Table Write Data Register Section 14 5 3 13 1813h SWE_DIFFSERV_TBL_RD_DATA Switch E...

Page 315: ... Section 14 5 3 31 1852h SWE_FILTERED_CNT_2 Switch Engine Port 2 Ingress Filtered Count Register Section 14 5 3 32 1853h 1854h RESERVED Reserved for Future Use 1855h SWE_INGRESS_REGEN_TBL_MII Switch Engine Port 0 Ingress VLAN Priority Regeneration Register Section 14 5 3 33 1856h SWE_INGRESS_REGEN_TBL_1 Switch Engine Port 1 Ingress VLAN Priority Regeneration Register Section 14 5 3 34 1857h SWE_IN...

Page 316: ...fer Manager Port 0 Egress Rate Priority Queue 0 1 Register Section 14 5 4 14 1C0Eh BM_EGRSS_RATE_02_03 Buffer Manager Port 0 Egress Rate Priority Queue 2 3 Register Section 14 5 4 15 1C0Fh BM_EGRSS_RATE_10_11 Buffer Manager Port 1 Egress Rate Priority Queue 0 1 Register Section 14 5 4 16 1C10h BM_EGRSS_RATE_12_13 Buffer Manager Port 1 Egress Rate Priority Queue 2 3 Register Section 14 5 4 17 1C11h...

Page 317: ...ion 1 4 08 19 08 DATASHEET 1C20h BM_IMR Buffer Manager Interrupt Mask Register Section 14 5 4 26 1C21h BM_IPR Buffer Manager Interrupt Pending Register Section 14 5 4 27 1C22h FFFFh RESERVED Reserved for Future Use Table 14 12 Indirectly Accessible Switch Control and Status Registers continued REGISTER SYMBOL REGISTER NAME ...

Page 318: ...tions of the switch fabric A list of the general switch CSRs and their corresponding register numbers is included in Table 14 12 14 5 1 1 Switch Device ID Register SW_DEV_ID This read only register contains switch device ID information including the device type chip version and revision codes Register 0000h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 16 Device Type Code DEVICE_...

Page 319: ...h Reset Register SW_RESET This register contains the switch fabric global reset Refer to Section 4 2 Resets on page 36 for more information Register 0001h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Switch Fabric Reset SW_RESET This bit is the global switch fabric reset All switch fabric blocks are affected This bit must be manually cleared WO 0b ...

Page 320: ... switch fabric interrupts due to the Buffer Manager via the Buffer Manager Interrupt Pending Register BM_IPR The status bits in the SW_IPR register are not affected R W 1b 5 Switch Engine Interrupt Mask SWE When set prevents the generation of switch fabric interrupts due to the Switch Engine via the Switch Engine Interrupt Pending Register SWE_IPR The status bits in the SW_IPR register are not aff...

Page 321: ... information Register 0005h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 7 RESERVED RO 6 Buffer Manager Interrupt BM Set when any unmasked bit in the Buffer Manager Interrupt Pending Register BM_IPR is triggered This bit is cleared upon a read RC 0b 5 Switch Engine Interrupt SWE Set when any unmasked bit in the Switch Engine Interrupt Pending Register SWE_IPR is triggered This bit is cleared upon...

Page 322: ...ns have been consolidated A lowercase x has been appended to the end of each switch port register name in this section where x should be replaced with MII 1 or 2 for the Port 0 Port 1 or Port 2 registers respectively A list of the Switch Port 0 Port 1 and Port 2 registers and their corresponding register numbers is included in Table 14 12 14 5 2 1 Port x MAC Version ID Register MAC_VER_ID_x This r...

Page 323: ...Receive Own Transmit When set the switch port will receive its own transmission if it is looped back from the PHY Normally this function is only used in Half Duplex PHY loopback R W 0b 4 RESERVED RO 3 Jumbo2K When set the maximum packet size accepted is 2048 bytes Statistics boundaries are also adjusted R W 0b 2 RESERVED RO 1 Reject MAC Types When set MAC control frames packets with a type field o...

Page 324: ...T_x This register provides a counter of undersized packets received by the port The counter is cleared upon being read Register Port0 0410h Size 32 bits Port1 0810h Port2 0C10h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Undersize Count of packets that have less than 64 byte and a valid FCS Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 1...

Page 325: ... cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Register Port0 0411h Size 32 bits Port1 0811h Port2 0C11h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 64 Bytes Count of packets including bad packets that have exactly 64 bytes Note This counter will stop a...

Page 326: ...nter is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Register Port0 0412h Size 32 bits Port1 0812h Port2 0C12h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 65 to 127 Bytes Count of packets including bad packets that have between 65 and 127 bytes Note Th...

Page 327: ...unter is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Register Port0 0413h Size 32 bits Port1 0813h Port2 0C13h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 128 to 255 Bytes Count of packets including bad packets that have between 128 and 255 bytes Note...

Page 328: ...nter is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Register Port0 0414h Size 32 bits Port1 0814h Port2 0C14h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 256 to 511 Bytes Count of packets including bad packets that have between 256 and 511 bytes Note ...

Page 329: ...unter is cleared upon being read Note A bad packet is defined as a packet that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes is rounded down to the nearest byte Register Port0 0415h Size 32 bits Port1 0815h Port2 0C15h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 512 to 1023 Bytes Count of packets including bad packets that have between 512 and 1023 bytes No...

Page 330: ...ter a packet with the maximum number of bytes that is not an integral number of bytes e g a 1518 1 2 byte packet is counted Register Port0 0416h Size 32 bits Port1 0816h Port2 0C16h BITS DESCRIPTION TYPE DEFAULT 31 0 RX 1024 to Max Bytes Count of packets including bad packets that have between 1024 and the maximum allowable number of bytes The max number of bytes is 1518 for untagged packets and 1...

Page 331: ... that is not an integral number of bytes e g a 1518 1 2 byte packet is not considered oversize Register Port0 0417h Size 32 bits Port1 0817h Port2 0C17h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Oversize Count of packets that have more than the maximum allowable number of bytes and a valid FCS The max number of bytes is 1518 for untagged packets and 1522 for tagged packets If Jumbo2K bit 3 is set in t...

Page 332: ...ived packets that are or proper length and are free of errors The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 0418h Size 32 bits Port1 0818h Port2 0C18h BITS DESCRIPTION TYPE DEFAULT 31 0 RX OK Count of packets that are of proper length and are free of errors Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollove...

Page 333: ...0 0419h Size 32 bits Port1 0819h Port2 0C19h BITS DESCRIPTION TYPE DEFAULT 31 0 RX CRC Count of packets that have between 64 and the maximum allowable number of bytes and have a bad FCS but do not have an extra nibble The max number of bytes is 1518 for untagged packets and 1522 for tagged packets If Jumbo2K bit 3 is set in the Port x MAC Receive Configuration Register MAC_RX_CFG_x the max number ...

Page 334: ...tination address The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Ah Size 32 bits Port1 081Ah Port2 0C1Ah BITS DESCRIPTION TYPE DEFAULT 31 0 RX Multicast Count of good packets proper length and free of errors including MAC control frames that have a multicast destination address not including broadcasts Note This counter will stop at ...

Page 335: ...ackets with a broadcast destination address The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Bh Size 32 bits Port1 081Bh Port2 0C1Bh BITS DESCRIPTION TYPE DEFAULT 31 0 RX Broadcast Count of valid packets proper length and free of errors that have a broadcast destination address Note This counter will stop at its maximum value of FFFF_...

Page 336: ... pause frame packets The counter is cleared upon being read Note A bad packet is one that has a FCS or Symbol error Register Port0 041Ch Size 32 bits Port1 081Ch Port2 0C1Ch BITS DESCRIPTION TYPE DEFAULT 31 0 RX Pause Frame Count of valid packets proper length and free of errors that have a type field of 8808h and an op code of 0001 Pause Note This counter will stop at its maximum value of FFFF_FF...

Page 337: ...is register provides a counter of received packets of less than 64 bytes and a FCS error The counter is cleared upon being read Register Port0 041Dh Size 32 bits Port1 081Dh Port2 0C1Dh BITS DESCRIPTION TYPE DEFAULT 31 0 RX Fragment Count of packets that have less than 64 bytes and a FCS error Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approx...

Page 338: ...not an integral number of bytes e g a 1518 1 2 byte packet and contains a FCS error is not considered jabber and is not counted here Register Port0 041Eh Size 32 bits Port1 081Eh Port2 0C1Eh BITS DESCRIPTION TYPE DEFAULT 31 0 RX Jabber Count of packets that have more than the maximum allowable number of bytes and a FCS error The max number of bytes is 1518 for untagged packets and 1522 for tagged ...

Page 339: ... of bytes e g a 1518 1 2 byte packet and a FCS error is considered an alignment error and is counted Register Port0 041Fh Size 32 bits Port1 081Fh Port2 0C1Fh BITS DESCRIPTION TYPE DEFAULT 31 0 RX Alignment Count of packets that have between 64 bytes and the maximum allowable number of bytes and are not byte aligned and have a bad FCS The max number of bytes is 1518 for untagged packets and 1522 f...

Page 340: ... 2048 bytes Jumbo2K 1 If this occurs the byte count recorded is 1518 1522 or 2048 respectively The Jumbo2K bit is located in the Port x MAC Receive Configuration Register MAC_RX_CFG_x Note A bad packet is one that has an FCS or Symbol error For this counter a packet that is not an integral number of bytes e g a 1518 1 2 byte packet is rounded down to the nearest byte Register Port0 0420h Size 32 b...

Page 341: ...ounter of total bytes received in good packets The counter is cleared upon being read Note A bad packet is one that has an FCS or Symbol error Register Port0 0421h Size 32 bits Port1 0821h Port2 0C21h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Good Bytes Count of total bytes received in good packets proper length and free of errors Note This counter will stop at its maximum value of FFFF_FFFFh Minimum ...

Page 342: ...X_SYMBOL_CNT_x This register provides a counter of received packets with a symbol error The counter is cleared upon being read Register Port0 0422h Size 32 bits Port1 0822h Port2 0C22h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Symbol Count of packets that had a receive symbol error Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 115 hour...

Page 343: ...ood packets with a type field of 8808h The counter is cleared upon being read Note A bad packet is one that has an FCS or Symbol error Register Port0 0423h Size 32 bits Port1 0823h Port2 0C23h BITS DESCRIPTION TYPE DEFAULT 31 0 RX Control Frame Count of good packets proper length and free of errors that have a type field of 8808h Note This counter will stop at its maximum value of FFFF_FFFFh Minim...

Page 344: ...ption of the Port x MAC Receive Packet Length Count Register MAC_RX_PKTLEN_CNT_x Port x MAC Transmit Packet Length Count Register MAC_TX_PKTLEN_CNT_x and Port x MAC Receive Good Packet Length Count Register MAC_RX_GOODPKTLEN_CNT_x counters which will be set to 7FFF_FF80h R W 0b 6 2 IFG Config These bits control the transmit inter frame gap IFG bit times IFG Config 4 12 R W 10101b 1 TX Pad Enable W...

Page 345: ...ter Port0 0441h Size 32 bits Port1 0841h Port2 0C41h BITS DESCRIPTION TYPE DEFAULT 31 18 RESERVED RO 17 16 Backoff Reset RX TX Half duplex only Determines when the truncated binary exponential backoff attempts counter is reset 00 Reset on successful transmission IEEE standard 01 Reset on successful reception 1X Reset on either successful transmission or reception R W 00b 15 0 Pause Time Value The ...

Page 346: ...d Register Port0 0451h Size 32 bits Port1 0851h Port2 0C51h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Deferred Count of packets that were available for transmission but were deferred on the first transmit attempt due to network traffic either on receive or prior transmission This counter is not incremented on collisions This counter is incremented only in half duplex operation Note This counter will s...

Page 347: ...ster MAC_TX_PAUSE_CNT_x This register provides a counter of transmitted pause packets The counter is cleared upon being read Register Port0 0452h Size 32 bits Port1 0852h Port2 0C52h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Pause Count of pause packets transmitted Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 481 hours RC 00000000h ...

Page 348: ... This register provides a counter of successful transmissions The counter is cleared upon being read Register Port0 0453h Size 32 bits Port1 0853h Port2 0C53h BITS DESCRIPTION TYPE DEFAULT 31 0 TX OK Count of successful transmissions Undersize packets are not included in this count Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 481 ...

Page 349: ...X_64_CNT_x This register provides a counter of 64 byte packets transmitted by the port The counter is cleared upon being read Register Port0 0454h Size 32 bits Port1 0854h Port2 0C54h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 64 Bytes Count of packets that have exactly 64 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 481 hours RC...

Page 350: ...x This register provides a counter of transmitted packets between the size of 65 to 127 bytes The counter is cleared upon being read Register Port0 0455h Size 32 bits Port1 0855h Port2 0C55h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 65 to 127 Bytes Count of packets that have between 65 and 127 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is appr...

Page 351: ...x This register provides a counter of transmitted packets between the size of 128 to 255 bytes The counter is cleared upon being read Register Port0 0456h Size 32 bits Port1 0856h Port2 0C56h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 128 to 255 Bytes Count of packets that have between 128 and 255 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is a...

Page 352: ... This register provides a counter of transmitted packets between the size of 256 to 511 bytes The counter is cleared upon being read Register Port0 0457h Size 32 bits Port1 0857h Port2 0C57h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 256 to 511 Bytes Count of packets that have between 256 and 511 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is ap...

Page 353: ... This register provides a counter of transmitted packets between the size of 512 to 1023 bytes The counter is cleared upon being read Register Port0 0458h Size 32 bits Port1 0858h Port2 0C58h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 512 to 1023 Bytes Count of packets that have between 512 and 1023 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is...

Page 354: ...ster provides a counter of transmitted packets between the size of 1024 to the maximum allowable number bytes The counter is cleared upon being read Register Port0 0459h Size 32 bits Port1 0859h Port2 0C59h BITS DESCRIPTION TYPE DEFAULT 31 0 TX 1024 to Max Bytes Count of packets that have more than 1024 bytes Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 1...

Page 355: ...er of undersized packets transmitted by the port The counter is cleared upon being read Register Port0 045Ah Size 32 bits Port1 085Ah Port2 0C5Ah BITS DESCRIPTION TYPE DEFAULT 31 0 TX Undersize Count of packets that have less than 64 bytes Note This condition could occur when TX padding is disabled and a tag is removed Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover...

Page 356: ...ter provides a counter of total bytes transmitted The counter is cleared upon being read Register Port0 045Ch Size 32 bits Port1 085Ch Port2 0C5Ch BITS DESCRIPTION TYPE DEFAULT 31 0 TX Bytes Count of total bytes transmitted does not include bytes from collisions but does include bytes from Pause packets Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps...

Page 357: ... MAC_TX_BRDCST_CNT_x This register provides a counter of transmitted broadcast packets The counter is cleared upon being read Register Port0 045Dh Size 32 bits Port1 085Dh Port2 0C5Dh BITS DESCRIPTION TYPE DEFAULT 31 0 TX Broadcast Count of broadcast packets transmitted Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately 481 hours RC 000...

Page 358: ..._x This register provides a counter of transmitted multicast packets The counter is cleared upon being read Register Port0 045Eh Size 32 bits Port1 085Eh Port2 0C5Eh BITS DESCRIPTION TYPE DEFAULT 31 0 TX Multicast Count of multicast packets transmitted including MAC Control Pause frames Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time at 100Mbps is approximately...

Page 359: ... of transmitted packets which experienced a late collision The counter is cleared upon being read Register Port0 045Fh Size 32 bits Port1 085Fh Port2 0C5Fh BITS DESCRIPTION TYPE DEFAULT 31 0 TX Late Collision Count of transmitted packets that experienced a late collision This counter is incremented only in half duplex operation Note This counter will stop at its maximum value of FFFF_FFFFh Minimum...

Page 360: ...er of transmitted packets which experienced 16 collisions The counter is cleared upon being read Register Port0 0460h Size 32 bits Port1 0860h Port2 0C60h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive Collision Count of transmitted packets that experienced 16 collisions This counter is incremented only in half duplex operation Note This counter will stop at its maximum value of FFFF_FFFFh Minimu...

Page 361: ...transmitted packets which experienced exactly 1 collision The counter is cleared upon being read Register Port0 0461h Size 32 bits Port1 0861h Port2 0C61h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive Collision Count of transmitted packets that experienced exactly 1 collision This counter is incremented only in half duplex operation Note This counter will stop at its maximum value of FFFF_FFFFh ...

Page 362: ...tted packets which experienced between 2 and 15 collisions The counter is cleared upon being read Register Port0 0462h Size 32 bits Port1 0862h Port2 0C62h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Excessive Collision Count of transmitted packets that experienced between 2 and 15 collisions This counter is incremented only in half duplex operation Note This counter will stop at its maximum value of FF...

Page 363: ...es a counter of total collisions including late collisions The counter is cleared upon being read Register Port0 0463h Size 32 bits Port1 0863h Port2 0C63h BITS DESCRIPTION TYPE DEFAULT 31 0 TX Total Collision Total count of collisions including late collisions This counter is incremented only in half duplex operation Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover ...

Page 364: ... be masked via this register An interrupt is masked by setting the corresponding bit of this register Clearing a bit will unmask the interrupt Refer to Chapter 5 System Interrupts on page 49 for more information Note There are no possible Port x interrupt conditions available This register exists for future use and should be configured as indicated for future compatibility Register Port0 0480h Siz...

Page 365: ...Port x interrupts A set bit indicates an interrupt has been triggered All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register MAC_IPR_x register Refer to Chapter 5 System Interrupts on page 49 for more information Note There are no possible Port x interrupt conditions available This register exists for future use Register Port0 0481h Size 32 bits Port1 0881h Por...

Page 366: ...s register The Make Pending bit in the Switch Engine ALR Command Status Register SWE_ALR_CMD_STS register indicates when the command is finished Refer to Chapter 6 Switch Fabric on page 55 for more information Register 1800h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 Make Entry When set the contents of ALR_WR_DAT_0 and ALR_WR_DAT_1 are written into the ALR table The ALR logic de...

Page 367: ...te Data 1 Register SWE_ALR_WR_DAT_1 and contains the first 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR Command Register SWE_ALR_CMD Register 1801h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 MAC Address This field contains the first 32 bits of the ALR entry that will be written into the ALR table These bits correspond to the first 32 bits of t...

Page 368: ...with a destination address that matches the MAC address in the SWE_ALR_WR_DAT_1 and SWE_ALR_WR_DAT_0 registers will be forwarded regardless of the port state of the ingress or egress port s This is typically used to allow the reception of BPDU packets in the non forwarding state R W 0b 22 Static When this bit is set this entry will not be removed by the aging process and or be changed by the learn...

Page 369: ...ld contains the last 16 bits of the ALR entry that will be written into the ALR table They correspond to the last 16 bits of the MAC address Bit 15 holds the MSB of the last byte the last bit on the wire The first 32 bits of the MAC address are located in the Switch Engine ALR Write Data 0 Register SWE_ALR_WR_DAT_0 R W 0000h BITS DESCRIPTION TYPE DEFAULT VALUE ASSOCIATED PORT S 000 Port 0 Host MAC...

Page 370: ... first 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register SWE_ALR_CMD This register is only valid when either of the Valid or End of Table bits in the Switch Engine ALR Read Data 1 Register SWE_ALR_RD_DAT_1 are set Register 1805h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 MAC Address This field contains the first...

Page 371: ...ble This bit stays cleared when the top of the ALR table is reached without finding an entry RO 0b 23 End of Table This bit indicates that the end of the ALR table has been reached and further Get Next Entry commands are not required Note The Valid bit may or may not be set when the end of the table is reached RO 0b 22 Static Indicates that this entry will not be removed by the aging process When ...

Page 372: ...MAC Address These field contains the last 16 bits of the ALR entry They correspond to the last 16 bits of the MAC address Bit 15 holds the MSB of the last byte the last bit on the wire The first 32 bits of the MAC address are located in the Switch Engine ALR Read Data 0 Register SWE_ALR_RD_DAT_0 RO 0000h BITS DESCRIPTION TYPE DEFAULT VALUE ASSOCIATED PORT S 000 Port 0 Host MAC 001 Port 1 010 Port ...

Page 373: ...nitialized Register 1808h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 2 RESERVED RO 1 ALR Init Done When set indicates that the ALR table has finished being initialized by the reset process The initialization is performed upon any reset that resets the switch fabric The initialization takes approximately 20uS During this time any received packet will be dropped Software should monitor this bit b...

Page 374: ... 08 19 08 374 SMSC LAN9312 DATASHEET 14 5 3 7 Switch Engine ALR Configuration Register SWE_ALR_CFG This register controls the ALR aging timer duration Register 1809h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 ALR Age Test When set this bit decreases the aging timer from 5 minutes to 50mS R W 0b ...

Page 375: ...Read Data Register SWE_VLAN_RD_DATA can then be read For a write access the Switch Engine VLAN Write Data Register SWE_VLAN_WR_DATA register should be written first The Operation Pending bit in the Switch Engine VLAN Command Status Register SWE_VLAN_CMD_STS indicates when the command is finished Register 180Bh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 6 RESERVED RO 5 VLAN RnW This bit specifie...

Page 376: ...er Port 2 Indicates the configuration of Port 2 for this VLAN entry 1 Member Packets with a VID that matches this entry are allowed on ingress The port is a member of the broadcast domain on egress 0 Not a Member Packets with a VID that matches this entry are filtered on ingress unless the Admit Non Member bit in the Switch Engine Admit Non Member Register SWE_ADMT_N_MEMBER is set for this port Th...

Page 377: ...LAN table entry as follows RO 00000h BITS DESCRIPTION DEFAULT 17 Member Port 2 Indicates the configuration of Port 2 for this VLAN entry 1 Member Packets with a VID that matches this entry are allowed on ingress The port is a member of the broadcast domain on egress 0 Not a Member Packets with a VID that matches this entry are filtered on ingress unless the Admit Non Member bit in the Switch Engin...

Page 378: ...4 5 3 11 Switch Engine VLAN Command Status Register SWE_VLAN_CMD_STS This register indicates the current VLAN command status Register 1810h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Operation Pending When set this bit indicates that the read or write command is taking place This bit is cleared once the command has finished RO SC 0b ...

Page 379: ...Register SWE_DIFFSERV_TBL_CMD_STS indicates when the command is finished The Switch Engine DIFFSERV Table Read Data Register SWE_DIFFSERV_TBL_RD_DATA can then be read For a write access the Switch Engine DIFFSERV Table Write Data Register SWE_DIFFSERV_TBL_WR_DATA register should be written first The Operation Pending bit in the Switch Engine DIFFSERV Table Command Status Register SWE_DIFFSERV_TBL_...

Page 380: ...IFFSERV_TBL_WR_DATA This register is used to write the DIFFSERV table The DIFFSERV table is not initialized upon reset on power up If DIFFSERV is enabled the full table should be initialized by the host Register 1812h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS CS field that matches thi...

Page 381: ...EET 14 5 3 14 Switch Engine DIFFSERV Table Read Data Register SWE_DIFFSERV_TBL_RD_DATA This register is used to read the DIFFSERV table Register 1813h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS CS field that matches this index RO 000b ...

Page 382: ...itch Engine DIFFSERV Table Command Status Register SWE_DIFFSERV_TBL_CMD_STS This register indicates the current DIFFSERV command status Register 1814h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Operation Pending When set this bit indicates that the read or write command is taking place This bit is cleared once the command has finished RO SC 0b ...

Page 383: ...ng When set IPv4 IGMP packets are snooped and sent to the MLD IGMP snoop port R W 0b 6 SWE Counter Test When this bit is set the Switch Engine counters that normally clear to 0 when read will be set to 7FFF_FFFCh when read R W 0b 5 DA Highest Priority When this bit is set and the Static bit in the ALR table for the destination MAC address is set the transmit priority queue that is selected is take...

Page 384: ...LAN9312 DATASHEET 1 VL Higher Priority When this bit is set and VLANs are enabled the priority from the VLAN tag has higher priority than the IP TOS SC field R W 1b 0 VLAN Enable When set VLAN ingress rules are enabled This also enables the VLAN to be used as the transmit priority queue selection R W 0b BITS DESCRIPTION TYPE DEFAULT ...

Page 385: ...orrespond to switch ports 2 1 0 respectively R W 111b 2 0 Enable Membership Checking When set VLAN membership is checked when a packet is received on the corresponding port The packet will be filtered if the ingress port is not a member of the VLAN unless the Admit Non Member bit is set for the port in the Switch Engine Admit Non Member Register SWE_ADMT_N_MEMBER For destination addresses that are...

Page 386: ...rt ingress rule for allowing only VLAN tagged packets Register 1842h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 Admit Only VLAN When set untagged and priority tagged packets are filtered The VLAN Enable bit in the Switch Engine Global Ingress Configuration Register SWE_GLOBAL_INGRSS_CFG needs to be set for these bits to have an affect There is one enable bit per ingress port B...

Page 387: ... RESERVED RO 5 4 Port State Port 2 These bits specify the spanning tree port states for Port 2 00 Forwarding 01 Blocking 10 Learning 11 Listening R W 00b 3 2 Port State Port 1 These bits specify the spanning tree port states for Port 1 00 Forwarding 01 Blocking 10 Learning 11 Listening R W 00b 1 0 Port State Port 0 These bits specify the spanning tree port states for Port 0 Host MAC 00 Forwarding ...

Page 388: ... queue that is used for packets with a priority of 6 R W 11b 11 10 Priority 5 traffic Class These bits specify the egress queue that is used for packets with a priority of 5 R W 10b 9 8 Priority 4 traffic Class These bits specify the egress queue that is used for packets with a priority of 4 R W 10b 7 6 Priority 3 traffic Class These bits specify the egress queue that is used for packets with a pr...

Page 389: ...Count Registers will still count these packets as filtered and the Switch Engine Interrupt Pending Register SWE_IPR will still register a drop interrupt R W 0b 7 5 Sniffer Port These bits specify the sniffer port that transmits packets that are monitored Bits 7 6 5 correspond to switch ports 2 1 0 respectively Note Only one port should be set as the sniffer R W 00b 4 2 Mirrored Port These bits spe...

Page 390: ...gister 1847h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 6 RESERVED RO 5 4 Ingress Port Type Port 2 A setting of 11b enables the usage of the VLAN tag to specify the packet destination All other values disable this feature R W 00b 3 2 Ingress Port Type Port 1 A setting of 11b enables the usage of the VLAN tag to specify the packet destination All other values disable this feature R W 00b 1 0 Ing...

Page 391: ...on Port 2 R W 0b 25 18 Broadcast Throttle Level Port 2 These bits specify the number of bytes x 64 allowed to be received per every 1 72mS interval R W 02h 17 Broadcast Throttle Enable Port 1 This bit enables broadcast input rate throttling on Port 1 R W 0b 16 9 Broadcast Throttle Level Port 1 These bits specify the number of bytes x 64 allowed to be received per every 1 72mS interval R W 02h 8 Br...

Page 392: ...egister is used to allow access to a VLAN even if the ingress port is not a member Register 1849h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 0 Admit Non Member When set a received packet is accepted even if the ingress port is not a member of the destination VLAN The VLAN still must be active in the switch There is one bit per ingress port Bits 2 1 0 correspond to switch ports 2...

Page 393: ...cessible via the Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD is used to configure the ingress rate metering coloring Register 184Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 3 RESERVED RO 2 1 Rate Mode These bits configure the rate metering coloring mode 00 Source Port Priority 01 Source Port Only 10 Priority Only 11 RESERVED R W 00b 0 Ingress Rate Enable When set ingress r...

Page 394: ...s BITS DESCRIPTION TYPE DEFAULT 31 8 RESERVED RO 7 Ingress Rate RnW These bits specify a read 1 or write 0 command R W 0b 6 5 Type These bits select between the ingress rate metering color table registers as follows 00 RESERVED 01 Committed Information Rate Registers uses CIS Address field 10 Committed Burst Register 11 Excess Burst Register R W 00b 4 0 CIR Address These bits select one of the 24 ...

Page 395: ...xcess Burst token buckets are initialized to this default value If a lower value is programmed into this register the token buckets will need to be normally depleted below this value before this value has any affect on limiting the token bucket maximum values This register is 16 bits wide R W 0600h Committed Burst Size This register specifies the maximum committed burst size in bytes Bursts larger...

Page 396: ...7 Switch Engine Ingress Rate Command Status Register SWE_INGRSS_RATE_CMD_STS This register indicates the current ingress rate command status Register 184Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Operation Pending When set indicates that the read or write command is taking place This bit is cleared once the command has finished RO SC 0b ...

Page 397: ...TE_WR_DATA This register is used to write the ingress rate table registers Register 184Dh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 Data This is the data to be written to the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD Refer to Section 14 5 3 26 1 Ingress Rate Table Registers on page 395 for details on the...

Page 398: ...S_RATE_RD_DATA This register is used to read the ingress rate table registers Register 184Eh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 0 Data This is the read data from the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD Refer to Section 14 5 3 26 1 Ingress Rate Table Registers on page 395 for details on these r...

Page 399: ...tered at ingress on Port 0 Host MAC This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register 1850h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Filtered This field is a count of packets filtered at ingress and is cleared when read Note This counter will stop at its maximum value of FF...

Page 400: ... filtered at ingress on Port 1 This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register 1851h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Filtered This field is a count of packets filtered at ingress and is cleared when read Note This counter will stop at its maximum value of FFFF_FF...

Page 401: ... filtered at ingress on Port 2 This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting which are counted separately Register 1852h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Filtered This field is a count of packets filtered at ingress and is cleared when read Note This counter will stop at its maximum value of FFFF_FF...

Page 402: ...CRIPTION TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priority 6 R W 6h 17 15 Regen5 These bits specify the regenerated priority for received priority 5 R W 5h 14 12 Regen4 These bits specify the regenerated priority for received priority 4 R W 4h 11 9 Reg...

Page 403: ...RIPTION TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priority 6 R W 6h 17 15 Regen5 These bits specify the regenerated priority for received priority 5 R W 5h 14 12 Regen4 These bits specify the regenerated priority for received priority 4 R W 4h 11 9 Rege...

Page 404: ...RIPTION TYPE DEFAULT 31 24 RESERVED RO 23 21 Regen7 These bits specify the regenerated priority for received priority 7 R W 7h 20 18 Regen6 These bits specify the regenerated priority for received priority 6 R W 6h 17 15 Regen5 These bits specify the regenerated priority for received priority 5 R W 5h 14 12 Regen4 These bits specify the regenerated priority for received priority 4 R W 4h 11 9 Rege...

Page 405: ... the number of MAC addresses on Port 0 Host MAC that were not learned or were overwritten by a different address due to address table space limitations Register 1858h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover ...

Page 406: ...nts the number of MAC addresses on Port 1 that were not learned or were overwritten by a different address due to address table space limitations Register 1859h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time a...

Page 407: ...nts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different address due to address table space limitations Register 185Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover time a...

Page 408: ... in the Switch Engine Interrupt Pending Register SWE_IPR All Switch Engine interrupts are masked by setting the Interrupt Mask bit Clearing this bit will unmask the interrupts Refer to Chapter 5 System Interrupts on page 49 for more information Register 1880h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Interrupt Mask When set this bit masks interrupts from the Switch Engine The s...

Page 409: ...ble but the source port was not in the forwarding state 0011 The destination address was found in the ALR table but the destination port was not in the forwarding state 0100 The destination address was found in the ALR table but Enable Membership Checking on ingress was set and the destination port was not a member of the incoming VLAN 0101 The destination address was found in the ALR table but th...

Page 410: ...d When set bits 14 9 are valid RC 0b 7 4 Drop Reason A When bit 1 is set these bits indicate the reason a packet was dropped See the Drop Reason B description above for definitions of each value of this field RC 0h 3 2 Source port A When bit 1 is set these bits indicate the source port on which the packet was dropped 00 Port 0 01 Port 1 10 Port 2 11 RESERVED RC 00b 1 Set A Valid When set bits 7 2 ...

Page 411: ...to 7FFF_FFFC when read R W 0b 5 Fixed Priority Queue Servicing When set output queues are serviced with a fixed priority ordering When cleared output queues are serviced with a weighted round robin ordering R W 0b 4 2 Egress Rate Enable When set egress rate pacing is enabled Bits 4 3 2 correspond to switch ports 2 1 0 respectively R W 0b 1 Drop on Yellow When this bit is set packets that exceed th...

Page 412: ...TS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Drop Level Low These bits specify the buffer limit that can be used per ingress port during times when 2 or 3 ports are active Each buffer is 128 bytes Note A port is active when 36 buffers are in use for that port R W 49h 7 0 Drop Level High These bits specify the buffer limit that can be used per ingress port during times when 1 port is active E...

Page 413: ...r backpressure is sent Register 1C02h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Pause Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active Each buffer is 128 bytes Note A port is active when 36 buffers are in use for that port R W 21h 7 0 Pause Level High These bits specify the buffer usage level during times when 1 port is active Ea...

Page 414: ...ause value of 1 is sent Register 1C03h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15 8 Resume Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active Each buffer is 128 bytes Note A port is active when 36 buffers are in use for that port R W 03h 7 0 Resume Level High These bits specify the buffer usage level during times when 0 or 1 ports are...

Page 415: ...dcast Buffer Level Register BM_BCST_LVL This register configures the buffer usage limits for broadcasts multicasts and unknown unicasts Register 1C04h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 8 RESERVED RO 7 0 Broadcast Drop Level These bits specify the maximum number of buffers that can be used by broadcasts multicasts and unknown unicasts Each buffer is 128 bytes R W 31h ...

Page 416: ...ffer Manager that were received on Port 0 Host MAC This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C05h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 0 and is cleared when read Note The counter will stop at its maximum value of FF...

Page 417: ...e Buffer Manager that were received on Port 1 This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C06h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 1 and is cleared when read Note The counter will stop at its maximum value of FFFF_FF...

Page 418: ...e Buffer Manager that were received on Port 2 This count includes packets dropped due to buffer space limits and ingress rate limit discarding Red and random Yellow dropping Register 1C07h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 2 and is cleared when read Note The counter will stop at its maximum value of FFFF_FF...

Page 419: ...en initialized by the reset process Note 14 63 The default value of this bit is 0 immediately following any switch fabric reset and then self sets to 1 once the ALR table is initialized Register 1C08h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 BM Ready When set indicates the Buffer Manager tables have finished being initialized by the reset process The initialization is performe...

Page 420: ...m Discard Table Write Data Register BM_RNDM_DSCRD_TBL_WDATA should be written before writing this register Register 1C09h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 5 RESERVED RO 4 Random Discard Weight Table RnW Specifies a read 1 or a write 0 command R W 0b 3 0 Random Discard Weight Table Index Specifies the buffer usage range that is accessed There are a total of 16 probability entries Each ...

Page 421: ...initialized by the host Register 1C0Ah Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 10 RESERVED RO 9 0 Drop Probability These bits specify the discard probability of a packet that has been colored Yellow by the ingress metering The probability is given in 1 1024 s For example a setting of 1 is one in 1024 or approximately 0 1 A setting of all ones 1023 is 1023 in 1024 or approximately 99 9 There ...

Page 422: ...T 31 10 RESERVED RO 9 0 Drop Probability These bits specify the discard probability of a packet that has been colored Yellow by the ingress metering The probability is given in 1 1024 s For example a setting of 1 is one in 1024 or approximately 0 1 A setting of all ones 1023 is 1023 in 1024 or approximately 99 9 There are a total of 16 probability entries Each entry corresponds to a range of the n...

Page 423: ...he egress port The Change Tag bit also needs to be set The un tag bit in the VLAN table for the incoming VLAN ID also needs to be cleared otherwise the tag will be removed instead Priority tagged packets will have VLAN ID overwritten with the Default VLAN ID of the ingress port independent of this bit This is only used when the Egress Port Type is set as Hybrid R W 0b 19 Change Priority Port 2 Whe...

Page 424: ...n above R W 0b 4 Change VLAN ID Port 0 Host MAC Identical to Change VLAN ID Port 2 definition above R W 0b 3 Change Priority Port 0 Host MAC Identical to Change Priority Port 2 definition above R W 0b 2 Change Tag Port 0 Host MAC Identical to Change Tag Port 2 definition above R W 0b 1 0 Egress Port Type Port 0 Host MAC Identical to Egress Port Type Port 2 definition above R W 0b BITS DESCRIPTION ...

Page 425: ...figure the egress rate pacing Register 1C0Dh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 0 Priority Queue 1 These bits specify the egress data rate for the Port 0 Host MAC priority queue 1 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 0 Priority Queue 0 These bits specify the egress data rate...

Page 426: ...figure the egress rate pacing Register 1C0Eh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 0 Priority Queue 3 These bits specify the egress data rate for the Port 0 Host MAC priority queue 3 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 0 Priority Queue 2 These bits specify the egress data rate...

Page 427: ...ed to configure the egress rate pacing Register 1C0Fh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 1 Priority Queue 1 These bits specify the egress data rate for the Port 1 priority queue 1 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 1 Priority Queue 0 These bits specify the egress data rate...

Page 428: ...ed to configure the egress rate pacing Register 1C10h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 1 Priority Queue 3 These bits specify the egress data rate for the Port 1 priority queue 3 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 1 Priority Queue 2 These bits specify the egress data rate...

Page 429: ...ed to configure the egress rate pacing Register 1C11h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 2 Priority Queue 1 These bits specify the egress data rate for the Port 2 priority queue 1 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 2 Priority Queue 0 These bits specify the egress data rate...

Page 430: ...ed to configure the egress rate pacing Register 1C12h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 26 RESERVED RO 25 13 Egress Rate Port 2 Priority Queue 3 These bits specify the egress data rate for the Port 2 priority queue 3 The rate is specified in time per byte The time is this value plus 1 times 20nS R W 00000h 12 0 Egress Rate Port 2 Priority Queue 2 These bits specify the egress data rate...

Page 431: ... BM_VLAN_MII This register is used to specify the default VLAN ID and priority of Port 0 Host MAC Register 1C13h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress R W 000b 11 0 Default VLAN ID These bits specify the default that is used when a tag is inserted or change...

Page 432: ...gister BM_VLAN_1 This register is used to specify the default VLAN ID and priority of Port 1 Register 1C14h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress R W 000b 11 0 Default VLAN ID These bits specify the default that is used when a tag is inserted or changed on ...

Page 433: ...gister BM_VLAN_2 This register is used to specify the default VLAN ID and priority of Port 2 Register 1C15h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 15 RESERVED RO 14 12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress R W 000b 11 0 Default VLAN ID These bits specify the default that is used when a tag is inserted or changed on ...

Page 434: ...number of packets received on Port 0 Host MAC that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C16h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 0 Host MAC and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimu...

Page 435: ...nts the number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C17h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 1 and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover...

Page 436: ...nts the number of packets received on Port 2 that were dropped by the Buffer Manager due to ingress rate limit discarding Red and random Yellow dropping Register 1C18h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Dropped Count These bits count the number of dropped packets received on Port 2 and is cleared when read Note This counter will stop at its maximum value of FFFF_FFFFh Minimum rollover...

Page 437: ...in the Buffer Manager Interrupt Pending Register BM_IPR All Buffer Manager interrupts are masked by setting the Interrupt Mask bit Clearing this bit will unmask the interrupts Refer to Chapter 5 System Interrupts on page 49 for more information Register 1C20h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 1 RESERVED RO 0 Interrupt Mask When set this bit masks interrupts from the Buffer Manager The ...

Page 438: ...en bit 7 is set these bits indicate the source port on which the packet was dropped 00 Port 0 01 Port 1 10 Port 2 11 RESERVED RC 00b 7 Status B Pending When set bits 13 8 are valid RC 0b BIT VALUES DESCRIPTION 0000 The destination address was not in the ALR table unknown or broadcast and the Broadcast Buffer Level was exceeded 0001 Drop on Red was set and the packet was colored Red 0010 There were...

Page 439: ... is set these bits indicate the reason a packet was dropped See the Drop Reason B description above for definitions of each value of this field RC 0h 2 1 Source port A When bit 0 is set these bits indicate the source port on which the packet was dropped 00 Port 0 01 Port 1 10 Port 2 11 RESERVED RC 00b 0 Set A Valid When set bits 6 1 are valid RC 0b BITS DESCRIPTION TYPE DEFAULT ...

Page 440: ...plies exhibit voltage spikes on their outputs when AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used Note 15 2 This rating does not apply to the following pins XI XO EXRES Note 15 3 This rating does not apply to the following pins EXRES Stresses exceeding those liste...

Page 441: ... supply voltage as well as external source sink current requirements Table 15 1 Supply and Current 10BASE T Full Duplex PARAMETER TYPICAL 3 3V MAXIMUM 3 6V UNIT Supply current at 3 3V VDD33A1 VDD33A2 VDD33BIAS VDD33IO 165 185 mA Power Dissipation Device Only 550 670 mW Power Dissipation Device and Ethernet components 1245 1435 mW Ambient Operating Temperature in Still Air TA 25 Note 15 4 oC Table ...

Page 442: ...39 345 10 1 18 1 6 420 3 6 1 35 1 8 485 10 3 V V V V mV uA pF Schmitt trigger Schmitt trigger Note 15 5 O8 Type Buffers Low Output Level High Output Level VOL VOH VDD33IO 0 4 0 4 V V IOL 8mA IOH 8mA OD8 Type Buffer Low Output Level VOL 0 4 V IOL 8mA O12 Type Buffer Low Output Level High Output Level VOL VOH VDD33IO 0 4 0 4 V V IOL 12mA IOH 12mA OD12 Type Buffer Low Output Level VOL 0 4 V IOL 12mA ...

Page 443: ... Note The I2C timing adheres to the Philips I2 C Bus Specification Refer to the Philips I2 C Bus Specification for detailed I2C timing information 15 5 1 Equivalent Test Load Output timing specifications assume the 25pF equivalent test load illustrated in Figure 15 1 below Overshoot and Undershoot VOS 5 Jitter 1 4 nS Note 15 9 Table 15 5 10BASE T Transceiver Characteristics PARAMETER SYMBOL MIN TY...

Page 444: ...od specified Please refer to Section 4 2 Resets on page 36 for additional information Note Device configuration straps are latched as a result of nRST assertion Refer to Section 4 2 4 Configuration Straps on page 40 for details Figure 15 2 nRST Reset Pin Timing Table 15 6 nRST Reset Pin Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS trstia nRST input assertion time 200 μS tcss Configuration st...

Page 445: ...uirements must be met Note Configuration straps must only be pulled high or low Configuration straps must not be driven as inputs Note Device configuration straps are also latched as a result of nRST assertion Refer to Section 15 5 2 Reset and Configuration Strap Timing on page 444 and Section 4 2 4 Configuration Straps on page 40 for additional details Figure 15 3 Power On Configuration Strap Lat...

Page 446: ...and nRD are de asserted These signals may be asserted and de asserted in any order Figure 15 4 PIO Read Cycle Timing Table 15 8 PIO Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Read Cycle Time 45 nS tcsl nCS nRD Assertion Time 32 nS tcsh nCS nRD De assertion Time 13 nS tcsdv nCS nRD Valid to Data Valid 30 nS tasu Address setup to nCS nRD Valid 0 nS tah Address Hold Time 0 n...

Page 447: ...ay be asserted and de asserted in any order Note Fresh data is supplied each time A 2 toggles Figure 15 5 PIO Burst Read Cycle Timing Table 15 9 PIO Burst Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcsh nCS nRD De assertion Time 13 nS tcsdv nCS nRD Valid to Data Valid 30 nS tacyc Address Cycle Time 45 nS tasu Address Setup to nCS nRD Valid 0 nS tadv Address Stable to Data Valid ...

Page 448: ...nd nRD are de asserted They may be asserted and de asserted in any order Figure 15 6 RX Data FIFO Direct PIO Read Cycle Timing Table 15 10 RX Data FIFO Direct PIO Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Read Cycle Time 45 nS tcsl CS nRD Assertion Time 32 nS tcsh nCS nRD De assertion Time 13 nS tcsdv nCS nRD Valid to Data Valid 30 nS tasu Address FIFO_SEL Setup to nCS n...

Page 449: ...sserted and de asserted in any order Note Fresh data is supplied each time A 2 toggles Figure 15 7 RX Data FIFO Direct PIO Burst Read Cycle Timing Table 15 11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcsh nCS nRD De assertion Time 13 nS tcsdv nCS nRD Valid to Data Valid 30 nS tacyc Address Cycle Time 45 nS tasu Address FIFO_SEL Setup to nCS nRD Va...

Page 450: ...The cycle ends when either or both nCS and nWR are de asserted These signals may be asserted and de asserted in any order Figure 15 8 PIO Write Cycle Timing Table 15 12 PIO Write Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Write Cycle Time 45 nS tcsl nCS nWR Assertion Time 32 nS tcsh nCS nWR De assertion Time 13 nS tasu Address Setup to nCS nWR Assertion 0 nS tah Address Hold T...

Page 451: ...d The cycle ends when either or both nCS and nWR are de asserted They may be asserted and de asserted in any order Figure 15 9 TX Data FIFO Direct PIO Write Cycle Timing Table 15 13 TX Data FIFO Direct PIO Write Cycle Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Write Cycle Time 45 nS tcsl nCS nWER Assertion Time 32 nS tcsh nCS nWR De assertion Time 13 nS tasu Address FIFO_SEL Setup t...

Page 452: ...CLK cycle time 1110 1130 nS tckh EECLK high time 550 570 nS tckl EECLK low time 550 570 nS tcshckh EECS high before rising edge of EECLK 1070 nS tcklcsl EECLK falling edge to EECS low 30 nS tdvckh EEDO valid before rising edge of EECLK 550 nS tckhdis EEDO disable after rising edge of EECLK 550 nS tdsckh EEDI setup to rising edge of EECLK 90 nS tdhckh EEDI hold after rising edge of EECLK 0 nS tckld...

Page 453: ...quency Deviation Over Time is also referred to as Aging Note 15 13 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802 3 as 50 PPM Note 15 14 This number includes the pad the bond wire and the lead frame PCB capacitance is not included in this value The XO XI pin and PCB capacitance values are required to accurately calculate the value of the two external load capacito...

Page 454: ...2 128 VTQFP Package Definition Table 16 1 LAN9312 128 VTQFP Dimensions MIN NOMINAL MAX REMARKS A 1 20 Overall Package Height A1 0 05 0 15 Standoff A2 0 95 1 00 1 05 Body Thickness D E 15 80 16 00 16 20 X Y Span D1 E1 13 80 14 00 14 20 X Y Plastic Body Size L 0 45 0 60 0 75 Lead Foot Length b 0 13 0 18 0 23 Lead Width c 0 09 0 20 Lead Foot Thickness e 0 40 BSC Lead Pitch ddd 0 00 0 07 True Position...

Page 455: ...y to the flat section of the lead foot between 0 10 and 0 25mm from the lead tip The base metal is exposed at the lead tip 3 Dimensions D1 and E1 do not include mold protrusions Maximum allowed protrusion is 0 25mm per side D1 and E1 are maximum plastic body size dimensions including mold mismatch 4 The pin 1 identifier may vary but is always located within the zone indicated Figure 16 2 LAN9312 1...

Page 456: ...e Two Port 10 100 Managed Ethernet Switch with 32 Bit Non PCI CPU Interface Datasheet Revision 1 4 08 19 08 456 SMSC LAN9312 DATASHEET 16 2 128 XVTQFP Package Outline Figure 16 3 LAN9312 128 XVTQFP Package Definition ...

Page 457: ...ismatch 4 Dimensions D2 and E2 represent the size of the exposed pad The exposed pad shall be coplanar with the bottom of the package within 0 05mm 5 The pin 1 identifier may vary but is always located within the zone indicated Table 16 2 LAN9312 128 XVTQFP Dimensions MIN NOMINAL MAX REMARKS A 1 20 Overall Package Height A1 0 05 0 15 Standoff A2 0 95 1 00 1 05 Body Thickness D E 15 80 16 00 16 20 ...

Page 458: ...ia the WUEN bit of the HMAC_WUCSR register a broadcast wake up frame will wake up the device despite the state of the Disable Broadcast Frames BCAST bit in the HMAC_CR register HMAC_WUCSR register Fixed error in GUE bit description the MAC Address 1 0 bits changed to the MAC Address 0 bits Port x PHY Special Control Status Register PHY_SPECIAL_CONTROL _STATUS_x on page 306 Updated RESERVED bits 11...

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