High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
251
Revision 1.4 (08-19-08)
DATASHEET
14.2.8.4
Virtual PHY Identification LSB Register (VPHY_ID_LSB)
This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI).
The MSB of the Virtual PHY OUI is contained in the
Virtual PHY Identification MSB Register
Note 14.25
The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
Note 14.26
IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.
Offset:
Index (decimal):
1CCh
3
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
(See
)
RO
-
15:10
PHY ID
This field contains the lower 6-bits of the Virtual PHY OUI (
).
R/W
00h
9:4
Model Number
This field contains the 6-bit manufacturer’s model number of the Virtual PHY
(
).
R/W
00h
3:0
Revision Number
This field contain the 4-bit manufacturer’s revision number of the Virtual PHY
(
).
R/W
0h