SingMai Electronics
PT9 User Manual Revision 0.3
Page 19 of 38
8.
Register interface
Figure 14 shows the timing diagram for the register interface; it is a conventional microprocessor
interface. Each register is selected via a 6-bit address bus. Writes to unused register locations are
ignored.
To write to the selected register the PT9_CSn (chip select) input must be asserted low, A[5:0]
assigned the required register address and the data for this register set up. The PT9_WRn input
must then be driven low and high again: On the rising edge of this pulse the data is latched into
the address selected. The PT9_CSn should then be returned high.
For the write to occur reliably the address (A[5:0]) and data (Din[7:0]) must be stable and valid
during the low to high transition of the PT9_WRn pulse.
The address input also selects the register data that is presented on the PT9_Register_out[7:0]
bus. This output is independent of the PT9_CSn or PT9_WRn inputs.
Figure 14 Control interface Timing.
