SingMai Electronics
PT9 User Manual Revision 0.3
Page 11 of 38
6.
Technical Overview
A simplified block diagram of the PT9 PAL encoder is shown in Figure 3.
Figure 3 PT9 Block Diagram.
The following is a brief description of the PT9 modules.
PT9_encoder.v
The top level module provides the interconnections to the other modules in the IP core.
PT9_Register_control.v
This module provides the register interface for the PT9. Chapter 8 provides a description of the
interface and Chapter 9 provides a description of the registers.
PT9_BT656_receiver.v
The input to the encoder is an 8 or 10 bit BT656 formatted data stream and associated 27MHz
clock. If the input is 8 bits the bottom 2 bits should be tied to logic ‘0’.
The 656 interface block identifies and extracts the TRS codes from the stream and de-multiplexes
and co-times the Y,Cb,Cr data.
This module also detects the line standard of the input BT656 video which can be used to auto
select the output video standard.
PT9_SPG.v
The clock, frame and active video signals from the BT656 receiver are used to synchronise a sync
pulse generator (SPG). The principal purpose of the SPG is to generate a compatible composite
sync output but it also generates the PAL switch signal (7.8kHz), the Bruch Blanking sequence for
PAL burst blanking, the Burst gate signal for inserting the colour burst into the output data and
the video blanking pulse.
