SingMai Electronics
PT9 User Manual Revision 0.3
Page 5 of 38
1.
Introduction
PT9 is a broadcast quality, multi-standard, video encoder supporting PAL-M/N/B/D/G/H/I and NTSC-
M/J outputs.
The intellectual property block accepts BT656 formatted data, in either 8 or 10 bit format, with the
associated 27MHz clock, and it encodes this data to a 10 bit, digital composite video output at
27MHz, which can be used to directly drive a digital to analogue converter, modulator or other
output device.
PT9 includes special cross-colour reduction circuitry, particularly of help in reducing artifacts when
used with a line comb video decoder.
The encoder can also be set to a free-run mode in which it ignores the BT656 timing information
and data and uses the clock input to generate a black and burst output.
Control and status registers are written to and read from using a conventional 8 bit wide
microprocessor interface.
The Altera FPGA usage (taken from the SM05 evaluation board compilation statistics) is shown in
Table 1.
Logic Elements
Memory Bits
M9K blocks
9x9 Multipliers
18x18 multipliers
9323
218112
25
1
41
Table 1 PT9 Altera FPGA resource requirements
The ASIC equivalent gate count is approximately 112k gates. The memory constitutes:
1 512 x 24 = 12288 bit single port ROM
4 2048 x 11 bit single port RAM = 90112 bits.
2 2048 x 10 bit single port RAM = 40960 bits.
2 2048 x 9 bit single port RAM = 36864 bits.
2 2048 x 12 bit single port RAM = 49152 bits.
