SingMai Electronics
PT9 User Manual Revision 0.3
Page 7 of 38
3.
Signal Interconnections
The PT9 signal interconnect diagram is shown in Figure 1.
Figure 1 PT9 Interconnection diagram.
The signal descriptions are shown in Table 3, below.
Signal
Description
Clock
27MHz clock input synchronous with the BT656 input data. The BT656
data should be stable at the rising edge of this clock.
Clock2x
54MHz clock input (2x Clock). The rising edge of this input should be
synchronous with the rising edge of Clock. This clock is used for the
single port RAM.
BT656_data[9..0]
BT656 compliant input data, sampled on the rising edge of Clock. If the
input is 8-bit the bottom 2 bits should be connected to ground (logic
‘0’).
RESETn
Asynchronous active low reset signal. Asserting this input sets all the
control registers to their default value and resets all registers.
A[5:0]
Control address bus input used to select the control register to be
written to/read from.
Din[7:0]
Control data input bus.
PT9_CSn
Control chip select input, active low. Used in combination with the WRn
input to control writing to the control registers.
PT9_WRn
Active low write enable input. Used in combination with the CSn input
to control writing to the control registers.
PT9_Register_out[7:0]
Control output data bus. Outputs the control/status register data
selected by the A[5:0] bus.
CVBS_out[9..0]
The digital composite output. The output format is straight binary with
bit 9 being the MSB. The output is valid on the rising edge of the Clock
input.
Comp_Sync
Composite sync signal output.
Table 3 Input/Output signals
