Simoco Xfin Blade, Service Manual

Page: 46 / 76

PAGE 46
TECHNICAL DESCRIPTION
4.3.5.1 DSP and FPGA
The Blade RF sub-assemblies operate under the control of a DSP (U102) and FPGA
(U106) combination which together with a number of other dedicated devices perform all
the operational and processing functions required by the radio. The FPGA is configured by
the DSP under software control to provide the following functions:
•
Channel set-up for operating frequency
•
Modulation processing and filtering
•
De-modulation processing and filtering
•
TX power output reference
•
Receiver front-end tuning
•
Serial communications with control board
•
Modem functionality for data modulation
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Embedded signalling / CTCSS generation and decoding
•
CO control
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Receiver muting control
•
TX / RX switching
•
PLL detect
4.3.5.2 DSP Clock Oscillator
The DSP is clocked by a 15.360MHz oscillator that consists of crystal X100 and an
internal DSP oscillator. Q100 forms a crystal switching circuit with C117 which when
activated by a command from the FPGA steers the oscillator away from potential
interfering frequencies.
4.3.6 RF Sub-Assembly Internal Memory
Memory consists of the internal DSP memory and an external 4MB non-volatile Flash
Memory U104. When power is off, program and data is retained in Flash Memory. At
power-on, a boot program downloads the DSP’s program from Flash Memory to its
internal RAM for faster program execution and access to data.
4.3.6.1 Multiplexer
U902 contains 2 separate 4-channel multiplexers providing a total of 8 independently
controlled analogue switches. Under software control, the multiplexers produce tuning
voltages from supplied data for the receiver front-end (TUNE 1 to 4), TX power setting (TX
PWR SET), receiver AGC (AGC-1), alert tone (A TONE) and FPGA ramp generator (ADC
REF).
Buffer U802B is fed with a composite digital tuning signal (AUX CTL) from the DSP/FPGA
containing the data for AGC, A TONE, ADC REF and TX PWR SET settings. The level is
dependent on channel frequency and tuning and varies between 0.1 to 3.0V. This signal is
applied to one group of 4 analogue switches in U902 via a common input connected to pin
13. The second group of 4 switches is fed with the receiver front-end tuning signal FE
TUNE (to provide outputs for TUNE 1 to 4) via the second common input at pin 3 as
described in the receiver front-end section.