Simoco Xfin Blade, Service Manual

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PAGE 42
TECHNICAL DESCRIPTION
4.3.4 Frequency Synthesis
4.3.4.1 General
Refer to Figure 3.7.
The SRM9000 frequency synthesiser consists of individual transmitter and receiver (local
oscillator) voltage controlled oscillators, loop filter, varactor negative bias generator,
reference oscillator and an integrated, dual phase locked loop device U701.
4.3.4.2 PLL
The PLL device contains two prescalers, programmable dividers and phase comparators
to provide a main and auxiliary PLL. The main PLL of U701 controls the frequency of the
TX/RX VCOs via Control Voltage outputs at pins 2 and 3 and VCO Feedback to pin 6. The
auxiliary PLL is used to control the receiver 90MHz second local oscillator via the Control
Voltage output at pin 17 and VCO Feedback to pin 15.
The PLL operation involves the division of the 14.4MHz reference oscillator frequency by
divider U710 and the internal divider of U701 down to a lower frequency which
corresponds to a sub-multiple of the radio channel spacing i.e. 6.25kHz for 12.5/25kHz
channel spacing or 5kHz for 20kHz channel spacing. The VCO frequency is sampled and
divided down to the same frequency after which it is phase compared to the reference.
Any error produces an offset to the Control Voltage output which is used to correct the
VCO frequency. A valid lock detect output is derived from pin 20 and is sampled by the
FPGA during transmit. If an unlocked signal is detected the radio will switch back to
receive mode.
4.3.4.3 VCO
The transmitter and receiver VCOs use low noise JFET transistors (Q600 RX, Q602 TX)
and inductors L602 (RX), L608 (TX) to generate the signals for the required band
coverage. Electronic tuning is provided by varactor diodes D600 to D608 with their control
voltages derived from the Loop Filter, PLL and Negative Bias Generator. VCO selection
and timing is controlled by the DSP via the RX and TX power supplies and applied through
switches Q601 (RX) and Q603 (TX). VCO buffer Q604/605 isolates the VCO from load
variations and active power supply filter Q615 minimises supply related noise. A PLL
feedback signal is sampled from the VCO buffer output via buffer Q607.
4.3.4.4 Negative Bias Generator and Loop Filter
A positive and negative varactor bias supply similar to the front-end varactor arrangement
has been used to achieve the required broadband tuning range of the VCOs. PLL device
U701 is programmed to deliver a fixed n2.5V output from phase detector/charge
pump CPPF or CPP (selection depends on radio setup) regardless of the channel
frequency selected. This voltage is filtered to remove synthesiser noise and reference
products by loop filter C719/722/734 and R721/724/734. The resulting low noise voltage is
applied to the cathode side of the VCO varactor tuning diodes as a positive bias voltage.
The negative bias supply originates as a positive DC voltage (0.1V to 3.0V) at the DAC
output of U701 (DOUT) with a level relative to the programmed state of the radio (e.g.
channel frequency, TX/RX state). The voltage is converted to a high level negative supply
by VCO Varicap Negative Supply Q700 to Q703. The -17V rail of this supply is generated