A N 3 3 2
104
Rev. 0.8
Property 0x1502. FM_RDS_CONFIG
Configures RDS settings to enable RDS processing (RDSEN) and set RDS block error thresholds. When a RDS
Group is received, all block errors must be less than or equal the associated block error threshold for the group to
be stored in the RDS FIFO. If blocks with errors are permitted into the FIFO, the block error information can be
reviewed when the group is read using the FM_RDS_STATUS command. The CTS bit (and optional interrupt) is
set when it is safe to send the next command. This property may only be set or read when in powerup mode. The
default is 0x0000.
Note:
FM_RDS_CONFIG is supported in FMRX component 2.0 or later.
Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49
Default: 0x0000
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2 D1
D0
Name
BLETHA[1:0] BLETHB[1:0] BLETHC[1:0] BLETHD[1:0]
0
0
0
0
0
0
0
RDSEN
Bit
Name
Function
15:14
BLETHA[1:0]
Block Error Threshold BLOCKA.
0 = No errors.
1 = 1–2 bit errors detected and corrected.
2 = 3–5 bit errors detected and corrected.
3 = Uncorrectable.
13:12
BLETHB[1:0]
Block Error Threshold BLOCKB.
0 = No errors.
1 = 1–2 bit errors detected and corrected.
2 = 3–5 bit errors detected and corrected.
3 = Uncorrectable.
11:10
BLETHC[1:0]
Block Error Threshold BLOCKC.
0 = No errors.
1 = 1–2 bit errors detected and corrected.
2 = 3–5 bit errors detected and corrected.
3 = Uncorrectable.
9:8
BLETHD[1:0]
Block Error Threshold BLOCKD.
0 = No errors.
1 = 1–2 bit errors detected and corrected.
2 = 3–5 bit errors detected and corrected.
3 = Uncorrectable.
0
RDSEN
RDS Processing Enable.
1 = RDS processing enabled.
