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Silicon Laboratories Si47 Series, Programming Manual

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AN332

Rev. 0.8

103

Property 0x1500. FM_RDS_INT_SOURCE

Configures interrupt related to RDS. The CTS bit (and optional interrupt) is set when it is safe to send the next
command. This property may only be set or read when in powerup mode. The default is 0.

Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49

Default: 0x0000 

Property 0x1501. FM_RDS_INT_FIFO_COUNT

Sets the minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set. The maximum value is
25 for FRMX component 2.0 or later, and 14 for FMRX component 1.0. The CTS bit (and optional interrupt) is set
when it is safe to send the next command. This property may only be set or read when in powerup mode. Default is
0.

Note:

FM_RDS_INT_FIFO_COUNT is supported in FMRX component 2.0 or later.

Available in: Si4705/06, Si4721, Si4731/35/37/39, Si4741/43/45/49

Default: 0x0000

Range: 0–25

Bit

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6

D5

D4

D3

D2

D1

D0

Name

0

0

0

0

0

0

0

0

0

0

RDSNEW-

BLOCKB

RDSNEW-

BLOCKA

0

RDSSYNC-

FOUND

RDSSYN-

CLOST

RDSRECV

Bit

Name

Function

15:6

Reserved

Always write to 0.

5

RDSNEWBLOCKB

RDS New Block B Found (Si4706, Si474x, and Si4705/31/35/85-D50 and later 
only)

If set, generate an interrupt when Block B data is found or subsequently changed.

4

RDSNEWBLOCKA

RDS New Block A Found (Si4706,Si474x and Si4705/31/35/85-D50 and later only)

If set, generate an interrupt when Block A data is found or subsequently changed

3

Reserved

Always write to 0.

2

RDSSYNCFOUND

RDS Sync Found.

If set, generate RDSINT when RDS gains synchronization.

1

RDSSYNCLOST

RDS Sync Lost.

If set, generate RDSINT when RDS loses synchronization.

0

RDSRECV

RDS Received.

If set, generate RDSINT when RDS FIFO has at least FM_RDS_INT_FIFO_COUNT 
entries.

Bit

D15

D14

D13  D12  D11  D10 

D9 

D8 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

Name

0

0

0

0

0

0

0

0

RDSFIFOCNT[7:0]

Bit

Name

Function

7:0

RDSFIFOCNT

RDS FIFO Count.

Minimum number of RDS groups stored in the RDS FIFO before RDSRECV is set.

Summary of Contents for Si47 Series

Page 1: ...nd receive responses from the device using one of three serial protocols or bus modes 2 wire mode I2 C and SMBUS compatible 3 wire mode or SPI mode Section 6 Control Interface on page 224 describes the control interface in detail Section 7 Powerup on page 232 describes options for the sequencing of VDD and VIO power supplies selection of the desired bus mode provision of the reference clock RCLK a...

Page 2: ...er with SAME 3x3 Si4708 FM Receiver 2 5x2 5 Si4709 FM Receiver with RDS 2 5x2 5 Si4710 FM Transmitter 3x3 Si4711 FM Transmitter with RDS 3x3 Si4712 FM Transmitter with RPS 3x3 Si4713 FM Transmitter with RDS RPS 3x3 Si4720 FM Transceiver 3x3 Si4721 FM Transceiver with RDS 3x3 Si4730 AM FM Receiver 3x3 Si4731 AM FM Receiver with RDS 2 3x3 Si4734 AM SW LW FM Receiver 3x3 Si4735 AM SW LW FM Receiver w...

Page 3: ...47441 AM LW SW FM Receiver 4x4 Si47451 AM LW SW FM Receiver with RDS 4x4 Si47491 High Performance RDS Receiver 4x4 Si4784 FM Receiver 3x3 Si4785 FM Receiver with RDS 2 3x3 Table 1 Product Family Function Continued Notes 1 Si4706 Si4707 and Si474x are covered under NDA 2 High Performance RDS is available in Si4705 31 35 85 D50 and later ...

Page 4: ...e Mode 227 6 3 SPI Control Interface Mode 230 7 Powerup 232 7 1 Powerup from Device Memory 233 7 2 Powerup from a Component Patch 234 8 Powerdown 239 9 Digital Audio Interface 240 10 Timing 243 11 FM Transmitter 249 11 1 Audio Dynamic Range Control for FM Transmitter 249 11 2 Audio Pre emphasis for FM Transmitter 250 11 3 Audio Limiter for FM Transmitter 251 11 4 Maximizing Audio Volume for FM Tra...

Page 5: ...rnal reference clock GPO General purpose output CTS Clear to send STC Seek Tune Complete NVM Non volatile internal device memory Device Refers to the FM Transmitter AM FM SW LW WB Receiver System Controller Refers to the system microcontroller CMD Command byte COMMANDn Command register 16 bit in 3 Wire mode n 1 to 4 ARGn Argument byte n 1 to 7 STATUS Status byte RESPn Response byte n 1 to 15 RESPO...

Page 6: ...ent from the device to the system controller The third column describes the action Properties are special command arguments used to modify the default device operation and are generally configured immediately after power up Examples of properties are TX _PREEMPHASIS and REFCLK_FREQ A complete list of properties is available in 5 Commands and Properties Table 3 shows an example of setting the REFCL...

Page 7: ...s value All 0x14 GET_INT_STATUS Read interrupt status bits All 0x15 PATCH_ARGS Reserved command used for patch file downloads All 0x16 PATCH_DATA Reserved command used for patch file downloads All 0x30 TX_TUNE_FREQ Tunes to given transmit frequency All 0x31 TX_TUNE_POWER Sets the output power level and tunes the antenna capaci tor All 0x32 TX_TUNE_MEASURE Measure the received noise level at the sp...

Page 8: ...s are in 10 Hz incre ments Default is 675 6 75 kHz 0x02A3 All 0x2103 TX_RDS_DEVIATION2 Configures the RDS RBDS fre quency deviation level Units are in 10 Hz increments Default is 2 kHz 0x00C8 Si4711 13 21 0x2104 TX_LINE_INPUT_LEVEL Configures maximum analog line input level to the LIN RIN pins to reach the maximum deviation level programmed into the audio deviation property TX Audio Deviation Defa...

Page 9: ...ed to detect silence on the incoming audio 0x0000 All 0x2302 TX_ASQ_DURATION_LOW Configures the duration which the input audio level must be below the low threshold in order to detect a low audio condition 0x0000 All 0x2303 TX_ASQ_LEVEL_HIGH Configures high audio input level detection threshold This threshold can be used to detect activity on the incoming audio 0x0000 All 0x2304 TX_ASQ_DURATION_HI...

Page 10: ... to inform the receiver of a single alter nate frequency using AF Method A coding and is transmitted along with the RDS_PS Groups 0xE0E0 Si4711 13 21 0x2C07 TX_RDS_FIFO_SIZE2 Number of blocks reserved for the FIFO Note that the value written must be one larger than the desired FIFO size 0x0000 Si4711 13 21 Table 5 FM Transmitter Property Summary Continued Prop Name Description Default Available In...

Page 11: ...mmand 6 ERR Error 0 No error 1 Error 5 3 Reserved Values may vary 2 RDSINT RDS Interrupt 0 RDS interrupt has not been triggered 1 RDS interrupt has been triggered 1 ASQINT Signal Quality Interrupt 0 Signal quality measurement has not been triggered 1 Signal quality measurement has been triggered 0 STCINT Seek Tune Complete Interrupt 0 Tune complete has not been triggered 1 Tune complete has been t...

Page 12: ...O2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is complete when the CTS bit and optional interrupt is set Note To change function e g FM TX to FM RX issue the POWER_DOWN command to stop the current function then issue POWER_UP to s...

Page 13: ... STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 RESERVED 7 0 Reserved various values 5 7 ...

Page 14: ...CMD 0 0 0 1 0 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 PATCHH 7 0 Patc...

Page 15: ...nd is written GPO pins are powered down and not active during this state For optimal power down current GPO2 must be either internally driven low through GPIO_CTL command or externally driven low Note In FMTX component 1 0 and 2 0 a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode Note The following describes the state of all the pins when in...

Page 16: ...7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to modify See Section 5 1 2 FM RDS Transmitter Properties on page 31 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to modify See Section 5 1 2 FM RDS Transmitter Properties on page 3...

Page 17: ... write to 0 2 7 0 PROPH 7 0 Property Get High Byte This byte in combination with PROPL is used to specify the property to get 3 7 0 PROPL 7 0 Property Get Low Byte This byte in combination with PROPH is used to specify the property to get Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 X X X X X X X X RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0 Reserv...

Page 18: ...the STATUS byte and when using interrupts this command should be called after the interrupt is set to update the STATUS byte The command is complete when the CTS bit and optional interrupt is set This command may only be sent when in powerup mode Available in All Command arguments None Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 1 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 19: ...ommand clears the STC bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 48 Command Timing Parameters for the FM Transmitter on page 245 Available in All Command arguments Three Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 0 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write t...

Page 20: ...powerup mode The command clears the STC bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 48 Command Timing Parameters for the FM Transmitter on page 245 Available in All Command arguments Four Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 0 1 ARG1 0 0 0 0 0 0 0 0 ARG2 0 0 0 0 0 0 0 0 ARG3 RFdBµV 7 0 ARG4 ANTCAP 7 0 ARG Bit Nam...

Page 21: ... in powerup mode The command clears the STC bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 48 Command Timing Parameters for the FM Transmitter on page 245 Available in Si4712 13 20 21 Command arguments Four Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 ARG4 ANTCAP 7 0 AR...

Page 22: ... it is safe to send the next command This command may only be sent when in powerup mode Available in All Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 1 1 ARG1 0 0 0 0 0 0 0 INTACK ARG Bit Name Function 1 7 1 Reserved Always write to 0 1 0 INTACK Seek Tune Interrupt Clear If set this bit clears the seek tune complete interrupt status indica...

Page 23: ... 0 Reserved Returns various data 5 7 0 READRFdBµV 7 0 Read Power Returns the transmit output voltage setting 6 7 0 READANTCAP 7 0 Read Antenna Tuning Capacitor This byte will contain the current antenna tuning capacitor value 7 7 0 RNL 7 0 Read Received Noise Level Si4712 13 Only This byte will contain the receive level as the response to a TX Tune Mea sure command The returned value will be the l...

Page 24: ...y the OVERMOD bit in which case the host could reduce the audio level to the part If any of the OVERMOD IALH or IALL bits are set the ASQINT bit will also be set The ASQINT bit can be routed to a hardware interrupt via the GPO_IEN property Clearing the IALH or IALL interrupts will result in the TX_ASQ_DURATION_LOW or TX_ASQ_DURATION_HIGH counters being rearmed respectively to start another detecti...

Page 25: ...tput signal is above requested modulation level 1 1 IALH Input Audio Level Threshold Detect High 0 Input audio level high threshold not exceeded 1 Input audio level high threshold exceeded 1 0 IALL Input Audio Level Threshold Detect Low 0 Input audio level low threshold not exceeded 1 Input audio level low threshold exceeded 2 7 0 Reserved Returns various values 3 7 0 Reserved Returns various valu...

Page 26: ...4711 13 21 Command arguments Seven Response bytes Five Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 1 0 1 ARG1 FIFO 0 0 0 0 LDBUFF MTBUFF INTACK ARG2 RDSBH 7 0 ARG3 RDSBL 7 0 ARG4 RDSCH 7 0 ARG5 RDSCL 7 0 ARG6 RDSDH 7 0 ARG7 RDSDL 7 0 ARG Bit Name Function 1 7 FIFO Operate on FIFO If set the command operates on the FIFO buffer If cleared the command operates on the circular buffer 1 6 3 Reser...

Page 27: ...SXMIT CBUFXMIT FIFOXMIT CBUFWRAP FIFOMT RESP2 CBAVAIL 7 0 RESP3 CBUSED 7 0 RESP4 FIFOAVAIL 7 0 RESP5 FIFOUSED 7 0 RESP Bit Name Function 1 7 5 Reserved Values may vary 1 4 RDSPSXMIT Interrupt source RDS PS Group has been transmitted 1 3 CBUFXMIT Interrupt source RDS Group has been transmitted from the FIFO buffer 1 2 FIFOXMIT Interrupt source RDS Group has been transmitted from the circular buffer...

Page 28: ...SCHAR1 7 0 ARG4 PSCHAR2 7 0 ARG5 PSCHAR3 7 0 ARG Bit Name Function 1 7 5 Reserved Always write to 0 1 4 0 PSID 4 0 Selects which PS data to load 0 23 0 First 4 characters of PS0 1 Last 4 characters of PS0 2 First 4 characters of PS1 3 Last 4 characters of PS1 22 First 4 characters of PS11 23 Last 4 characters of PS11 2 7 0 PSCHAR0 7 0 RDS PSID CHAR0 First character of selected PSID 3 7 0 PSCHAR1 7...

Page 29: ...omponent 3 0 or later Only bit GPO3OEN is supported in FMTX comp 2 0 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Available in All except Si4710 A10 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN ...

Page 30: ...GPO pins set for high impedance Note GPIO_SET is fully supported in FMTX comp 3 0 or later Only bit GPO3LEVEL is supported in FMTX comp 2 0 Available in All except Si4710 A10 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Ou...

Page 31: ...ly 0 No interrupt generated when RDSINT is already set default 1 Interrupt generated even if RDSINT is already set 9 ASQREP ASQ Interrupt Repeat 0 No interrupt generated when ASQREP is already set default 1 Interrupt generated even if ASQREP is already set 8 STCREP STC Interrupt Repeat 0 No interrupt generated when STCREP is already set default 1 Interrupt generated even if STCREP is already set 7...

Page 32: ...1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 IFALL IMODE 3 0 IMONO ISIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 IFALL DCLK Falling Edge 0 Sample on DCLK rising edge default 1 Sample on DCLK falling edge 6 3 IMODE 3 0 Digital Mode 0000 default 0001 I2 S Mode 0111 Left justified mode 1101 MSB at 1st DCLK rising edge after DFS Pulse 1001 MSB at 2nd DCLK rising edge after ...

Page 33: ...his property may only be set or read when in powerup mode TX_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property Note DIGITAL_INPUT_SAMPLE_RATE is supported in FMTX component 2 0 or later Available in All except Si4710 A10 Default 0x0000 Units 1 Hz Step 1 Hz Range 0 32000 48000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 ...

Page 34: ...Figure 1 REFCLK Prescaler The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE TX_TUNE_FREQ or TX_TUNE_POWER commands In addition the RCLK must be valid at all times when the carrier is enabled for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property ma...

Page 35: ...tional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Available in All Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF 15 0 Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK frequency range is between 31130 and 3440...

Page 36: ...d when in powerup mode The default is 6825 or 68 25 kHz Available in All Default 0x1AA9 6825 Units 10 Hz Step 10 Hz Range 0 9000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RDS LMR PILOT Bit Name Function 15 3 Reserved Always write 0 2 RDS RDS Enable Si4711 13 21 Only 0 Disables RDS default 1 Enables RDS to be transmitted 1 LMR Left Minus Right 0 Disabl...

Page 37: ...t is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 200 or 2 kHz Available in Si4711 13 21 Default 0x00C8 200 Units 10 Hz Step 10 Hz Range 0 9000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TXPDEV 15 0 Bit Name Function 15 0 TXPDEV 15 0 Transmit Pilot Frequency Deviation Pilot tone frequency deviation is pro...

Page 38: ...aximum line level on RIN LIN below 636 mVPK The Line Level would be set to 636 mVPK to correspond to the TX audio deviation level set by the TX_AUDIO_DEVIATION property The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default input level and peak line level is 636 mVPK with an input impedance of 60 k A...

Page 39: ...This property may only be set or read when in powerup mode The default is 75 µs Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMUTE RIMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LIMUTE Mutes L Line Input 0 No mute default 1 Mute 0 RIMUTE Mutes R Line Input 0 No mute default 1 Mute Bit D15 D14 D13 D12 D11 D10...

Page 40: ... enables the audio dynamic range control and limiter The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is limiter enabled and audio dynamic range control disabled Note LIMITEN bit is supported in FMTX component 2 0 or later Reset this bit to 0 in FMTX component 1 0 Available in All Default 0x000...

Page 41: ...device applies the compression defined by gain threshold threshold The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0xFFD8 or 40 dBFS Available in All Default 0xFFD8 40 Units 1 dB Step 1 dB Range 40 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name THRESHOLD 15 0 Bit Name F...

Page 42: ...t is safe to send the next command This property may only be set or read when in powerup mode The default is 0 5 ms or 0 Available in All Default 0x0000 Range 0 9 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 ATTACK 3 0 Bit Name Function 15 4 Reserved Always write to 0 3 0 ATTACK 3 0 Transmit Audio Dynamic Range Control Attack Time 0 0 5 ms default 1 1 0 ms...

Page 43: ... to the audio below the threshold set by the TX_ACOMP_THRESHOLD property The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 15 dB or 0xF Available in All Default 0x000F 15 Units 1 dB Step 1 dB Range 0 20 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 R...

Page 44: ...is 5 01 ms or 102 Note TX_LIMITER_RELEASE_TIME is supported in FMTX component 2 0 or later Available in All except Si4710 A10 Default 0x0066 102 Step 1 Range 5 2000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name LIMITERTC 15 0 Bit Name Function 15 0 LMITERTC 15 0 Sets the limiter release time 5 102 39 ms 6 85 33 ms 7 73 14 ms 8 63 99 ms 10 51 19 ms 13 39 38 ms 17 30 11 ms 25 20 47 ...

Page 45: ... bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERMODIEN IALHIEN IALLIEN Bit Name Function 15 3 Reserved Always write to 0 2 OVERMODIEN Overmodulation Detection Enable 0 OVERMOD detect disab...

Page 46: ...35 ms and the default is 0 ms Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ TX_TUNE_POWER or TX_TUNE_MEASURE The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Available in All Default 0x0000 Un...

Page 47: ...and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0x0000 and the range is 0 to 70 Available in All Default 0x0000 Units 1 dB Step 1 dB Range 70 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 IALHTH 7 0 Bit Name Function 15 8 Reserved Always write to 0 7 0 IALHTH 7 0 I...

Page 48: ...and will only return valid data after a call to TX_TUNE_FREQ TX_TUNE_POWER or TX_TUNE_MEASURE The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Available in All Default 0x0000 Units 1 ms Step 1 ms Range 0 65535 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name IALHDUR 15 0 Bit Name Function 15 ...

Page 49: ...n a RDS PS Group has been transmitted The interrupt occurs when a PS group begins transmission 3 RDSCBUFXMIT 0 Do not interrupt default 1 Interrupt when a RDS Group has been transmitted from the Circular Buffer The interrupt occurs when a group is fetched from the buffer 2 RDSFIFOXMIT 0 Do not interrupt default 1 Interrupt when a RDS Group has been transmitted from the FIFO Buffer The interrupt oc...

Page 50: ...ay only be set or read when in powerup mode Note TX_RDS_PS_MIX is supported in FMTX component 2 0 or later Available in Si4711 13 21 Default 0x0003 Range 0 6 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSPI 15 0 Bit Name Function 15 0 RDSPI 15 0 Transmit RDS Program Identifier RDS program identifier data Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0...

Page 51: ...3 Dynamic PTY code 0 Static PTY default 1 Indicates that the PTY code is dynamically switched 14 RDSD2 Compressed code 0 Not compressed default 1 Compressed 13 RDSD1 Artificial Head code 0 Not artificial head default 1 Artificial head 12 RDSD0 Mono Stereo code 0 Mono 1 Stereo default 11 FORCEB Use the PTY and TP set here in all block B data 0 FIFO and BUFFER use PTY and TP as when written default ...

Page 52: ... is safe to send the next command This property may only be set or read when in powerup mode Note TX_RDS_PS_MESSAGE_COUNT is supported in FMTX component 2 0 or later Available in Si4711 13 21 Default 0x0001 Range 1 12 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSPSRC 7 0 Bit Name Function 15 8 Reserved Always write to 0 7 0 RDSPSRC 7 0 Transmit RDS PS Repeat Co...

Page 53: ... when it is safe to send the next command This property may only be set or read when in powerup mode Note TX_RDS_PS_AF is supported in FMTX component 2 0 or later Available in Si4711 13 21 Default 0xE0E0 Range 0xE000 0xE0CC Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSAF 15 0 Bit Name Function 15 0 RDSAF 15 0 Transmit RDS Program Service Alternate Frequency 0xE101 1 AF 87 6 MH...

Page 54: ...FIFO command as the buffer size may vary between versions or part numbers The guaranteed minimum FIFO size however is 53 blocks The RDS FIFO and the RDS Circular Buffer should be emptied with the TX_RDS_FIFO command prior to changing the size of the FIFO The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Not...

Page 55: ...nloads All 0x20 FM_TUNE_FREQ Selects the FM tuning frequency All 0x21 FM_SEEK_START Begins searching for a valid frequency All 0x22 FM_TUNE_STATUS Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command All 0x23 FM_RSQ_STATUS Queries the status of the Received Signal Quality RSQ of the current channel All 0x24 FM_RDS_STATUS Returns RDS information for current channel and reads an entr...

Page 56: ...FILTER Selects bandwidth of channel filter applied at the demodulation stage 0x0001 Si4706 Si4749 Si4705 31 35 85 D50 and later 0x0000 Si4704 30 34 84 D50 and later 0x1105 FM_BLEND_STEREO_ THRESHOLD Selects bandwidth of channel filter applied at the demodulation stage 0x0031 Si470x 2x Si473x C40 and earlier 0x1106 FM_BLEND_MONO_ THRESHOLD Sets RSSI threshold for mono blend Full mono below threshol...

Page 57: ... when entering and leaving soft mute 0x0040 Si4706 07 20 21 84 85 B20 and earlier Si4704 05 3x C40 and earlier 0x1301 FM_SOFT_MUTE_SLOPE Configures attenuation slope during soft mute in dB attenuation per dB SNR below the soft mute SNR threshold Default value is 2 0x0002 Si4704 05 06 3x C40 and later Si4740 41 42 43 44 45 0x1302 FM_SOFT_MUTE_ MAX_ATTENUATION Sets maximum attenuation during soft mu...

Page 58: ...0x0014 All 0x1500 FM_RDS_INT_SOURCE Configures RDS interrupt behavior 0x0000 Si4705 06 Si4721 Si431 35 37 39 Si4741 43 45 49 0x1501 FM_RDS_INT_FIFO_ COUNT Sets the minimum number of RDS groups stored in the receive FIFO required before RDSRECV is set 0x0000 Si4705 06 Si4721 Si431 35 37 39 Si4741 43 45 49 0x1502 FM_RDS_CONFIG Configures RDS setting 0x0000 Si4705 06 Si4721 Si431 35 37 39 Si4741 43 4...

Page 59: ...4 45 Si4705 31 35 85 D50 and later 0x1803 FM_BLEND_RSSI_ RELEASE_RATE Sets the mono to stereo release rate for RSSI based blend Smaller values provide slower release and larger values provide faster release The default is 400 approxi mately 164 ms 0x0190 Si4706 C30 and later Si4740 41 42 43 44 45 Si4705 31 35 85 D50 and later 0x1804 FM_BLEND_SNR_ STEREO_THRESHOLD Sets SNR threshold for stereo blen...

Page 60: ...low threshold blend above threshold To force stereo set this to 100 To force mono set this to 0 Default value is 20 0x0014 Si4740 41 42 43 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later 0x1809 FM_BLEND_MULTIPATH_M ONO_THRESHOLD Sets Multipath threshold for mono blend Full mono above threshold blend below threshold To force stereo set to 100 To force mono set...

Page 61: ...s 0x0018 Si4742 43 44 45 0x1902 FM_NB_RATE Noise blanking rate in 100 Hz units Default value is 64 0x0040 Si4742 43 44 45 0x1903 FM_NB_IIR_FILTER Sets the bandwidth of the noise floor esti mator Default value is 300 0x012C Si4742 43 44 45 0x1904 FM_NB_DELAY Delay in micro seconds before applying impulse blanking to the original samples Default value is 133 0x00AA Si4742 43 44 45 0x1A00 FM_HICUT_ S...

Page 62: ...704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later 0x1A05 FM_HICUT_ MULTIPATH_END_ THRESHOLD Sets the MULTIPATH level at which hi cut reaches maximum band limiting Default value is 60 0x003C Si4740 41 42 43 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later 0x1A06 FM_HICUT_ CUTOFF_FREQUENCY Sets the maximum band limit frequency for hi ...

Page 63: ...lues may vary 3 RSQINT Received Signal Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 RDSINT Radio Data System RDS Interrupt Si4705 21 31 35 37 39 85 Only 0 Radio data system interrupt has not been triggered 1 Radio data system interrupt has been triggered 1 Reserved Values may vary 0 STCINT Seek Tune Comple...

Page 64: ...B20 the POWER_UP command also configures the state of GPO3 DCLK pin 17 Si474x pin 19 DFS pin 16 Si474x pin 18 and DOUT pin 15 Si474x pin 17 for digital audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_I...

Page 65: ...00001011 Digital audio output DCLK LOUT DFS ROUT DIO 10110000 Digital audio outputs DCLK DFS DIO Si4705 21 31 35 37 39 41 43 45 84 85 FMRX component 2 0 or later with XOSCEN 0 10110101 Analog and digital audio outputs LOUT ROUT and DCLK DFS DIO Si4705 21 31 35 37 39 41 43 45 84 85 FMRX component 2 0 or later with XOSCEN 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Bit D7...

Page 66: ...2x 3x 4x Command Response 4 7 0 RESERVED 7 0 Reserved various values 5 7 0 RESERVED 7 0 Reserved various values 6 7 0 CHIPREV 7 0 Chip Revision ASCII 7 7 0 LIBRARYID 7 0 Library Revision HEX Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CM...

Page 67: ...RX component 1 0 a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode Note The following describes the state of all the pins when in powerdown mode GPIO1 GPIO2 and GPIO3 0 ROUT LOUT DOUT DFS HiZ Available in All Command arguments None Response bytes None Command Response RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number HEX 2 7 ...

Page 68: ...e bytes None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 0 ARG2 PROPH 7 0 ARG3 PROPL 7 0 ARG4 PROPDH 7 0 ARG5 PROPDL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to modify 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to...

Page 69: ...Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to get 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to get Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0...

Page 70: ...t if an invalid argument is sent Note that only a single interrupt occurs if both the CTS and ERR bits are set The optional STC interrupt is set when the command completes The STCINT bit is set only after the GET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STC bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and ...

Page 71: ... selects the tune frequency in 10 kHz In FM mode the valid range is from 6400 to 10800 64 108 MHz 3 7 0 FREQL 7 0 Tune Frequency Low Byte This byte in combination with FREQH selects the tune frequency in 10 kHz In FM mode the valid range is from 6400 to 10800 64 108 MHz 4 7 0 ANTCAP 7 0 Antenna Tuning Capacitor valid only when using TXO LPI pin as the antenna input This selects the value of the an...

Page 72: ...ET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STCINT bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 49 Command Timing Parameters for the FM Receiver on page 246 Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 0 0 1 ARG1 0 0 0 0 SEE...

Page 73: ...rup mode Available in All Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 0 1 0 ARG1 0 0 0 0 0 0 CANCEL INTACK ARG Bit Name Function 1 7 2 Reserved Always write to 0 1 1 CANCEL Cancel seek If set aborts a seek currently in progress 1 0 INTACK Seek Tune Interrupt Clear If set clears the seek tune complete interrupt status indicator Bit D7 D6 D5 ...

Page 74: ...L returns frequency being tuned 10 kHz 3 7 0 READFREQL 7 0 Read Frequency Low Byte This byte in combination with READFREQH returns frequency being tuned 10 kHz 4 7 0 RSSI 7 0 Received Signal Strength Indicator This byte contains the receive signal strength when tune is complete dBµV 5 7 0 SNR 7 0 SNR This byte contains the SNR metric when tune is complete dB 6 7 0 MULT 7 0 Multipath This byte cont...

Page 75: ...d by MULTLINT If the PILOT indicator is set it can also check whether the blend has crossed a threshold as indicated by BLENDINT The command clears the RSQINT BLENDINT SNRHINT SNRLINT RSSIHINT RSSILINT MULTHINT and MULTLINT interrupt bits when INTACK bit of ARG1 is set The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup m...

Page 76: ...len below SNR low threshold 1 Received SNR has fallen below SNR low threshold 1 1 RSSIHINT RSSI Detect High 0 RSSI has not exceeded above RSSI high threshold 1 RSSI has exceeded above RSSI high threshold 1 0 RSSILINT RSSI Detect Low 0 RSSI has not fallen below RSSI low threshold 1 RSSI has fallen below RSSI low threshold 2 3 SMUTE Soft Mute Indicator Indicates soft mute is engaged 2 1 AFCRL AFC Ra...

Page 77: ... 06 Si4721 Si474x Si4731 35 37 39 Si4785 Command arguments One Response bytes Twelve Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 1 0 0 ARG1 0 0 0 0 0 STATUSONLY MTFIFO INTACK ARG Bit Name Function 1 2 STATUSONLY Status Only Determines if data should be removed from the RDS FIFO 0 Data in BLOCKA BLOCKB BLOCKC BLOCKD and BLE contain the oldest data in the RDS FIFO 1 Data in BLOCKA wil...

Page 78: ...errun 2 0 RDSSYNC RDS Sync 1 RDS currently synchronized 3 7 0 RDSFIFOUSED RDS FIFO Used Number of groups remaining in the RDS FIFO 0 if empty If non zero BLOCKA BLOCKD contain the oldest FIFO entry and RDSFIFOUSED decre ments by one on the next call to RDS_FIFO_STATUS assuming no RDS data received in the interim 4 7 0 BLOCKA 15 8 RDS Block A Block A group data from oldest FIFO entry if STATUSONLY ...

Page 79: ...EB 1 0 RDS Block B Corrected Errors 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 bit errors detected and corrected 3 Uncorrectable 12 3 2 BLEC 1 0 RDS Block C Corrected Errors 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 bit errors detected and corrected 3 Uncorrectable 12 1 0 BLED 1 0 RDS Block D Corrected Errors 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 ...

Page 80: ...3 D2 D1 D0 CMD 0 0 1 0 0 1 1 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 X X X X X X X READ_RF AGCDIS RESP2 X X X READ_LNA_GAIN_INDEX 4 0 RESP Bit Name Function 1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled 2 4 0 READ_LNA_GAIN_INDEX These bits returns the value of the LNA GAIN index 0 Minimum at...

Page 81: ...d Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG2 X X X LNA_GAIN_INDEX 4 0 ARG Bit Name Function 1 0 RFAGCDIS This bit selects whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled 2 4 0 LNA_GAIN_INDEX These bits set the value of the LNA GAIN index 0 Minimum attenuation max gain 1 25 Intermediate attenuation 26 Maximum attenuation ...

Page 82: ...onent 2 0 or later Only bit GPO3OEN is supported in FMRX component 1 0 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Available in All except Si4710 A10 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OE...

Page 83: ...ins set for high impedance Note GPIO_SET is fully supported in FMRX component 2 0 or later Only bit GPO3LEVEL is supported in FMRX component 1 0 Available in All except Si4710 A10 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GP...

Page 84: ...SQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 RDSREP RDS Interrupt Repeat Si4705 21 31 35 37 39 41 43 45 85 C40 Only 0 No interrupt generated when RDSINT is already set default 1 Interrupt generated even if RDSINT is already set 9 Reserved Always write to 0 8 STCREP STC Interrupt Repeat 0 No interrupt generated when STCINT is already set default 1 Interrupt ge...

Page 85: ...0 or later Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 OFALL OMODE 3 0 OMONO OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 OFALL Digital Output DCLK Edge 0 use DCLK rising edge 1 use DCLK falling edge 6 3 OMODE 3 0 Digital Output Mode 0000 I2S 0110 Left justified 1000 MSB at second DCLK after DFS pulse 1100 MSB at first DCLK after DFS pulse 2 OMONO Digital Output...

Page 86: ...se the device will not respond and will require reset The sample rate must be set to 0 before the DCLK DFS is removed FM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property Note DIGITAL_OUPTUT_SAMPLE_RATE is supported in FM receive component 2 0 or later Available in Si4705 06 Si4721 31 35 37 39 Si4730 34 36 38 D60 and later Si4741 ...

Page 87: ...K_START commands In addition the RCLK must be valid at all times for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 32768 Hz Available in All Default 0x8000 32768 Units 1 Hz Step 1 Hz Range 31130 34406 Table 11 RCL...

Page 88: ... times for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Available in All Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL REFCLKP 11 0 Bit Name Fu...

Page 89: ...t is 1 Available in Si4706 Si4749 Si4704 05 30 31 34 35 84 85 D50 and later Default 0x0001 Si4706 Si4749 Si4705 31 35 85 D50 and later 0x0000 Si4704 30 34 84 D50 and later Range 0 4 Note Automatic channel filter setting is not supported in FMRX component 3 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEMPH 1 0 Bit Name Function 15 2 Reserved Always ...

Page 90: ...This property may only be set or read when in powerup mode The default is 30 dBµV Available in Si470x 2x Si473x C40 and earlier Default 0x001E Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STTHRESH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 STTHRESH FM Blend Stereo Threshold RSSI threshold below which the audio output ...

Page 91: ... may only be set or read when in powerup mode The default is 20 kHz Note For FMRX components 2 0 or earlier the default is set to 30 kHz For best seek performance set FM_MAX_TUNE_ERROR to 20 kHz Available in All Default 0x001E Si473x B20 and earlier 0x0014 all others Units kHz Step 1 Range 0 255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMTXO Bit ...

Page 92: ...05 30 31 34 35 84 85 D50 and later only Enable Multipath high as the source of interrupt which the threshold is set by FM_RSQ_MULTIPATH_HI_THRESHOLD 4 MULTLIEN Interrupt Source Enable Multipath Low Si4706 C30 and later Si474x and Si4704 05 30 31 34 35 84 85 D50 and later only Enable Multipath low as the source of interrupt which the threshold is set by FM_RSQ_MULTIPATH_LO_THRESHOLD 3 SNRHIEN Inter...

Page 93: ...mmand This property may only be set or read when in powerup mode The default is 0 dB Available in All Default 0x0000 Units dB Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SNRH FM RSQ SNR High Threshold Threshold which triggers the RSQ interrupt if the SNR is above this threshold Sp...

Page 94: ... This property may only be set or read when in powerup mode The default is 0 dBµV Available in All Default 0x0000 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 RSSIH FM RSQ RSSI High Threshold Threshold which triggers the RSQ interrupt if the RSSI is above this threshold...

Page 95: ...is threshold The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in power up mode The default is 0 Available in Si4706 C30 and later Si474x Si4704 05 30 31 34 35 84 85 D50 and later Default 0x0000 Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MULTH 6 0 Bit Name Function 1...

Page 96: ...erup mode The default is 0x0040 Available in Si4706 07 20 21 84 85 B20 and earlier Si4704 05 3x C40 and earlier Default 64 Step 1 Range 1 255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 PILOT BLEND 6 0 Bit Name Function 15 8 Reserved Always write to 0 7 PILOT Pilot Indicator This bit has to be set to 1 there has to be a pilot present in order for FM_RSQ_BLEND_THR...

Page 97: ...gurable in Si4710 20 A10 devices those with FMRX component 1 0 and is 0 dB dB disabled Available in Si4704 05 06 3x C40 and later Si4740 41 42 43 44 45 Default 0x0002 Range 0 63 Property 0x1302 FM_SOFT_MUTE_MAX_ATTENUATION Sets maximum attenuation during soft mute dB Set to 0 to disable soft mute The CTS bit and optional interrupt is set when it is safe to send the next command This property may o...

Page 98: ...slower release and larger values provide faster release The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 8192 approximately 8000 dB s Release Rate dB s RELEASE 14 0 1 024 Available in Si4706 C30 and later Si4740 41 42 43 44 45 Si4704 05 30 31 34 35 84 85 D50 and later Default 0x2000 Range 1 ...

Page 99: ...0 dB s Attack Rate dB s ATTACK 14 0 1 024 Available in Si4706 C30 and later Si4740 41 42 43 44 45 Si4704 05 30 31 34 35 84 85 D50 and later Default 0x2000 Range 1 32767 Figure 3 Softmute Gain dB Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 ATTACK 14 0 Softmute Gain dB 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SNR dB x 2 y 16 z 4 Default x 4 y 16 z 4 x 2 y 4...

Page 100: ...hen in powerup mode The default is 87 5 MHz Available in All Default 0x222E Units 10 kHz Step 50 kHz Range 64 108 MHz Note For FMRX components 2 0 or earlier range is 76 108 MHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMSKFREQL 15 0 Bit Name Function 15 0 FMSKFREQL FM Seek Band Bottom Frequency Selects the bottom of the FM Band during Seek Specified in units of 10 kHz Defaul...

Page 101: ...is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 100 kHz Available in All Default 0x000A Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMSKFREQH 15 0 Bit Name Function 15 0 FMSKFREQH FM Seek Band Top Frequency Selects the top of the FM Band during Seek Specified in units of 10 kHz Default is 10790 107 9 MHz B...

Page 102: ...mode The default is 20 dBµV Available in All Default 0x0014 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SKSNR 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SKSNR FM Seek Tune SNR Threshold SNR Threshold which determines if a valid channel has been found during Seek Tune Specified in units of dB in 1 dB steps 0 127 Defau...

Page 103: ...t D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 RDSNEW BLOCKB RDSNEW BLOCKA 0 RDSSYNC FOUND RDSSYN CLOST RDSRECV Bit Name Function 15 6 Reserved Always write to 0 5 RDSNEWBLOCKB RDS New Block B Found Si4706 Si474x and Si4705 31 35 85 D50 and later only If set generate an interrupt when Block B data is found or subsequently changed 4 RDSNEWBLOCKA RDS New Block A Fou...

Page 104: ...n Si4705 06 Si4721 Si4731 35 37 39 Si4741 43 45 49 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name BLETHA 1 0 BLETHB 1 0 BLETHC 1 0 BLETHD 1 0 0 0 0 0 0 0 0 RDSEN Bit Name Function 15 14 BLETHA 1 0 Block Error Threshold BLOCKA 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 bit errors detected and corrected 3 Uncorrectable 13 12 BLETHB 1 0 Block Error Thresh...

Page 105: ...r attack The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 4 approximately 1500 dB s Nominal 6000 is based on 50 source impedance and will vary with source impedance In most systems an exact value is not important However to calculate for a different source impedance perform the following ste...

Page 106: ...s 20 Record RF level with index equal 20 4 Replace 6000 in rate equation with RF20 RF0 0 00667 Available in Si4740 41 42 43 44 45 49 Default 0x008C Step 4 Range 4 248 Note Was property 0x4101 in FW2 B Property 0x1800 FM_BLEND_RSSI_STEREO_THRESHOLD Sets RSSI threshold for stereo blend Full stereo above threshold blend below threshold To force stereo set to 0 To force mono set to 127 The CTS bit and...

Page 107: ...2 FM_BLEND_RSSI_ATTACK_RATE Sets the stereo to mono attack rate for RSSI based blend Smaller values provide slower attack and larger values provide faster attack The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 4000 approximately 16 ms ATTACK 15 0 65536 time where time is the desired transit...

Page 108: ...E 15 0 65536 time where time is the desired transition time in ms Available in Si4706 C30 and later Si4740 41 42 43 44 45 Si4704 05 30 31 34 35 84 85 D50 and later Default 0x0190 Step 1 Range 0 disabled 1 32767 Figure 4 RSSI Blend Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE 15 0 Stereo 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 3...

Page 109: ... dB Step 1 Range 0 127 Property 0x1805 FM_BLEND_SNR_MONO_THRESHOLD Sets SNR threshold for mono blend Full mono below threshold blend above threshold To force stereo set to 0 To force mono set to 127 The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 14 dB Available in Si4740 41 42 43 44 45 Si4...

Page 110: ...Step 1 Range 0 disabled 1 32767 Property 0x1807 FM_BLEND_SNR_RELEASE_RATE Sets the mono to stereo release rate for SNR based blend Smaller values provide slower release and larger values provide faster release The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 400 approximately 164 ms RELEASE ...

Page 111: ...be set or read when in powerup mode The default is 20 Available in Si4740 41 42 43 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later Default 0x0014 Step 1 Range 0 100 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STRTHRESH 6 0 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SNR dB ...

Page 112: ...LTIPATH_ATTACK_RATE Sets the stereo to mono attack rate for Multipath based blend Smaller values provide slower attack and larger values provide faster attack The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 4000 approximately 16 ms ATTACK 15 0 65536 time where time is the desired transition...

Page 113: ...ately 1 64 s RELEASE 15 0 65536 time where time is the desired transition time in ms Available in Si4740 41 42 43 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later Default 0x0028 Step 1 Range 0 disabled 1 32767 Figure 6 MP Blend Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RELEASE 15 0 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 ...

Page 114: ...ult 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX_SEP 2 0 Bit Name Function 15 3 Reserved Always write to 0 2 0 MAX_SEP Maximum Stereo Separation 0 disabled default 1 12dB of separation maximum 2 15dB of separation maximum 3 18dB of separation maximum 4 21dB of separation maximum 5 24dB of separation maximum 6 27dB of separation maximum 7 30dB ...

Page 115: ...and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 24 µs Available in Si4742 43 44 45 Default 0x0018 Range 8 48 Note Was property 0x4107 in FW2 B Property 0x1902 FM_NB_RATE Noise blanking rate in 100 Hz units The CTS bit and optional interrupt is set when it is safe to send the next command This property ...

Page 116: ...1600 Note Was property 0x4109 in FW2 B Property 0x1904 FM_NB_DELAY Delay in micro seconds before applying impulse blanking to the original samples The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 170 µs Available in Si4742 43 44 45 Default 0x00AA Range 125 219 Note Was property 0x410A in FW2...

Page 117: ...Blanker Si4742 43 FM Impulse Noise Blanker time time time Blanker Input Blanker Output LPF IIR Output FM_NB_DETECT_THRESHOLD FM_NB_INTERVAL FM_NB_RATE sets maximum repeat rate NB is allowed to fire FM_NB_IIR_FILTER adjusts LPF FM_NB_DELAY ...

Page 118: ...3 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later Default 0x000F Range 0 127 Note Was property 0x180D in FW2 B Property 0x1A02 FM_HICUT_ATTACK_RATE Sets the rate at which hi cut lowers the transition frequency The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read in POWERUP mode The default is...

Page 119: ...roperty may only be set or read in POWERUP mode The default is 20 Available in Si4740 41 42 43 44 45 Si4704 05 D50 and later Si4706 C30 and later Si4730 31 34 35 84 85 D50 and later Default 0x0014 Range 0 100 Note Was property 0x1810 in FW2 B Property 0x1A05 FM_HICUT_MULTIPATH_END_THRESHOLD Sets the MULTIPATH level at which hi cut reaches maximum band limiting The CTS bit and optional interrupt is...

Page 120: ...D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MAXIMUM AUDIO FREQ 2 0 0 FREQUENCY 2 0 Bit Name Function 6 4 MAXIMUM AUDIO FREQUENCY 2 0 Maximum Audio Frequency 0 Maximum Audio transition frequency Max Audio BW 1 Maximum Audio transition frequency 2 kHz 2 Maximum Audio transition frequency 3 kHz 3 Maximum Audio transition frequency 4 kHz 4 Maximum Audio transition frequency 5 kHz ...

Page 121: ...z 0 w 0x1A00 FM_HICUT_SNR_HIGH_THRESHOLD 0 127 dB x 0x1A01 FM_HICUT_SNR_LOW_THRESHOLD 0 127 dB y 0x1A06 FM_HICUT_CUTOFF_FREQ 2 0 0 7 z 0x1A06 MAXIMUM AUDIO FREQ 6 4 0 7 0 1 2 3 4 5 6 7 8 9 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SNR dB Hi Cut Filter Transition Frequency kHz w 24 x 15 y 0 z 6 Default w 24 x 15 y 1 z 6 w 30 x 15 y 1 z 6 w 0x1A00 FM_HICUT_SNR_HIGH_THRESHOLD 0 127 dB...

Page 122: ...0 w 0x1A04 FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD 0 100 x 0x1A05 FM_HICUT_MULTIPATH_END_THRESHOLD 0 100 y 0x1A06 FM_HICUT_CUTOFF_FREQ 2 0 0 7 z 0x1A06 MAXIMUM AUDIO FREQ 6 4 0 7 0 1 2 3 4 5 6 7 8 9 0 10 20 30 40 50 60 70 80 90 100 Multipath Hi Cut Filter Transition Frequency kHz w 20 x 60 y 0 z 6 Default w 20 x 60 y 1 z 6 w 30 x 60 y 1 z 6 w 0x1A04 FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD 0 100 x 0x1A05...

Page 123: ...l interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is unmute 0x0000 Available in All except Si4749 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 VOL 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 VOL Output Volume Sets the output volume level 63 max 0 min D...

Page 124: ...GET_REV Returns revision information on the device All 0x11 POWER_DOWN Power down device All 0x12 SET_PROPERTY Sets the value of a property All 0x13 GET_PROPERTY Retrieves a property s value All 0x14 GET_INT_STATUS Read interrupt status bits All 0x15 PATCH_ARGS Reserved command used for patch file downloads All 0x16 PATCH_DATA Reserved command used for patch file downloads All 0x40 AM_TUNE_FREQ Tu...

Page 125: ... 2 5 1 8 or 1 kHz The default bandwidth is 2 kHz 0x0003 All 0x3103 AM_AUTOMATIC_ VOLUME_CONTROL_ MAX_GAIN Sets the maximum gain for automatic volume control 0x1543 Si473x C40 and later 0x7800 Si474x 0x3104 AM_MODE_AFC_SW_ PULL_IN_RANGE Sets the SW AFC pull in range 0x21F7 Si4734 35 C40 and later Si4742 43 44 45 0x3105 AM_MODE_AFC_SW_ LOCK_IN_RANGE Sets the SW AFC lock in 0x2DF5 Si4734 35 C40 and l...

Page 126: ... dB 0x000A Si4730 31 34 35 36 37 B20 and earlier Si4740 41 42 43 44 45 C10 and earlier 0x0008 All others 0x3304 AM_SOFT_MUTE_ RELEASE_RATE Sets softmute release rate Smaller values provide slower release and larger values provide faster release The default is 8192 approximately 8000 dB s 0x2000 Si4740 41 42 43 44 45 0x3305 AM_SOFT_MUTE_ ATTACK_RATE Sets software attack rate Smaller values provide ...

Page 127: ...3 44 45 only 0x130C Si4740 41 42 43 44 45 0x3900 AM_NB_DETECT_ THRESHOLD Sets the threshold for detecting impulses in dB above the noise floor Default value is 12 0x000C Si4742 43 44 45 0x3901 AM_NB_INTERVAL Interval in micro seconds that original samples are replaced by interpolated clean samples Default value is 55 µs 0x0037 Si4742 43 44 45 0x3902 AM_NB_RATE Noise blanking rate in 100 Hz units D...

Page 128: ... command 1 Clear to send next command 6 ERR Error 0 No error 1 Error 5 4 Reserved Values may vary 3 RSQINT Received Signal Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 1 Reserved Values may vary 0 STCINT Seek Tune Complete Interrupt 0 Tune complete has not been triggered 1 Tune complete has been triggered ...

Page 129: ... Si4731 35 37 the POWER_UP command also configures the state of GPO3 DCLK pin 17 DFS pin 16 and DOUT pin 15 for digital audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is compl...

Page 130: ...al audio outputs DCLK DFS DIO Si4731 35 37 only with XOSCEN 0 10110101 Analog and digital audio outputs LOUT ROUT and DCLK DFS DIO Si4731 35 37 only with XOSCEN 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RE...

Page 131: ...0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmware Minor Revision ASCII 4 7 0 PATCHH 7 0 Patch ID Hi...

Page 132: ...P command is written GPO pins are powered down and not active during this state For optimal power down current GPO2 must be either internally driven low through GPIO_CTL command or externally driven low Note In AMRX component 1 0 a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode Note The following describes the state of all the pins when in ...

Page 133: ... 7 0 ARG4 PROPDH 7 0 ARG5 PROPDL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to modify See Section 5 3 2 AM SW LW Receiver Properties on page 146 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to modify See Section 5 3 2 AM SW ...

Page 134: ...7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to get 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to get Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0 ...

Page 135: ...valid argument is sent Note that only a single interrupt occurs if both the CTS and ERR bits are set The optional STC interrupt is set when the command completes The STCINT bit is set only after the GET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STC bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 50 C...

Page 136: ...gh Byte This byte in combination with ANTCAPL selects the tuning capacitor value If both bytes are set to zero the tuning capacitor value is selected automatically If the value is set to anything other than 0 the tuning capacitance is manually set as 95 fF x ANTCAP 7 pF ANTCAP manual range is 1 6143 Automatic capacitor tuning is recom mended Note In SW mode ANTCAPH 15 8 needs to be set to 0 and AN...

Page 137: ...and ERR bits are set The optional STC interrupt is set when the command completes The STCINT bit is set only after the GET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STCINT bit if it is already set See Figure 29 CTS and STC Timing Model on page 244 and Table 50 Command Timing Parameters for the AM Receiver on page 247 Note ANTCAP bits are...

Page 138: ...is set to anything other than 0 the tuning capacitance is manually set as 95 fF x ANTCAP 7 pF ANTCAP manual range is 1 6143 Automatic capacitor tuning is recommended Note In SW mode ANTCAPH 15 8 needs to be set to 0 and ANTCAPL 7 0 needs to be set to 1 5 7 0 ANTCAPL 7 0 Antenna Tuning Capacitor Low Byte This byte in combination with ANTCAPH selects the tuning capacitor value If both bytes are set ...

Page 139: ...ot work properly on AMRX component 2 1 or earlier Available in All Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 0 0 1 0 ARG1 0 0 0 0 0 0 CANCEL INTACK ARG Bit Name Function 1 7 2 Reserved Always write to 0 1 1 CANCEL Cancel seek If set aborts a seek currently in progress 1 0 INTACK Seek Tune Interrupt Clear If set clears the seek tune complete...

Page 140: ...ency Low Byte This byte in combination with READFREQH returns frequency being tuned kHz 4 7 0 RSSI 7 0 Received Signal Strength Indicator This byte contains the receive signal strength when tune is completed dBµV 5 7 0 SNR 7 0 SNR This byte contains the SNR metric when tune is completed dB 6 7 0 READANTCAPH 15 8 Read Antenna Tuning Capacitor High Byte This byte in combination with READANTCAPL retu...

Page 141: ...SQINT SNRHINT SNRLINT RSSIHINT and RSSILINT interrupt bits when INTACK bit of ARG1 is set The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode Note AFCRL bit does not work properly on AMRX component 2 1 or earlier Available in All Command arguments One Response bytes Five Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 C...

Page 142: ...d 1 Received SNR has exceeded below SNR low threshold 1 1 RSSIHINT RSSI Detect High 0 RSSI has not exceeded above RSSI high threshold 1 RSSI has exceeded above RSSI high threshold 1 0 RSSILINT RSSI Detect Low 0 RSSI has not exceeded below RSSI low threshold 1 RSSI has exceeded below RSSI low threshold 2 3 SMUTE Soft Mute Indicator Indicates soft mute is engaged 2 1 AFCRL AFC Rail Indicator Set if ...

Page 143: ...Minimum attenuation max gain 1 36 ATTN_BACKUP Intermediate attenuation 37 ATTN_BACKUP Maximum attenuation min gain Note The max index is subject to change See Property 0x3705 AM_FRONTEND_AGC_CONTROL for details on ATTN_BACKUP Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 1 0 0 0 ARG1 0 0 0 0 0 0 0 AMAGCDIS ARG2 AMAGCNDX 7 0 ARG Bit Name Function 1 0 AMAGCDIS AM AGC Disable This bit selects whether the A...

Page 144: ...O_CTL is supported in AM_SW_LW component 2 0 or later 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1...

Page 145: ... powerup mode The default is all GPO pins set for high impedance Note GPIO_SET is supported in AM_SW_LW component 2 0 or later Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level 0 Output low default...

Page 146: ...STCIEN Bit Name Function 15 12 Reserved Always write to 0 11 RSQREP RSQ Interrupt Repeat 0 No interrupt generated when RSQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 9 Reserved Always write to 0 8 STCREP STC Interrupt Repeat 0 No interrupt generated when STCINT is already set default 1 Interrupt generated even if STCINT is already set 7 CTSIEN CTS Interrupt En...

Page 147: ...ter Si4741 43 45 Si4784 85 Default 0x0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 OFALL OMODE 3 0 0 OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 OFALL Digital Output DCLK Edge 0 use DCLK rising edge 1 use DCLK falling edge 6 3 OMODE 3 0 Digital Output Mode 0000 I2 S 0110 Left justified 1000 MSB at second DCLK after DFS pulse 1100 MSB at first DCLK after DFS ...

Page 148: ...ut else the device will not respond and will require reset The sample rate must be set to 0 before DCLK DFS is removed AM_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property Note DIGITAL_OUTPUT_SAMPLE_RATE is supported in AM_SW_LW component 2 0 or later Available in Si4705 06 Si4731 35 37 39 Si4730 34 36 38 D60 and later Si4741 43 4...

Page 149: ...t be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command In addition the RCLK must be valid at all times when the carrier is enabled for proper AGC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode The default is 32768 Hz Available ...

Page 150: ... to send the next command This property may only be set or read when in powerup mode The default is 1 Available in All Default 0x0001 Step 1 Range 1 4095 Note For shortwave frequencies choose a prescalar value such that you can limit the REFCLK frequency range to 31130 32768 Hz Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK frequency range is between 3113...

Page 151: ...74x devices AM_SW_LW component 3 0 or later The 2 5 kHz option is supported on Si473x C40 and later devices AM_SW_LW component 5 0 or later Available in All Default 0x0003 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEMPH Bit Name Function 15 1 Reserved Always write to 0 0 DEEMPH AM De Emphasis 1 50 µs 0 Disabled Bit D15 D14 D13 D12 D11 D10 D9 D8 D...

Page 152: ... would be equivalent to AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN property value 0x7800 which is the maximum value Available in Si473x C40 and later Si474x Default 0x1543 Si473x C40 and later 0x7800 Si474x Step 1 Range 0X1000 0x7800 Property 0x3104 AM_MODE_AFC_SW_PULL_IN_RANGE Sets the SW AFC pull in or tracking range The value PULL_IN_RANGE is relative to the tuned frequency and is specified as 1 PPM ...

Page 153: ... be set or read when in powerup mode Available in All Default 0x0000 Bit Name Function 15 0 SWPIR 15 0 SW Pull In Range The SW pull in range expressed relative to the tuned frequency Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SWPIR 15 0 Bit Name Function 15 0 SWPIR 15 0 SW Pull In Range The SW lock in range expressed relative to the tuned frequency Bit D15 D14 D13 D12 D11 D10 D...

Page 154: ...le RSSI High Enable RSSI low as the source of interrupt which the threshold is set by AM_RSQ_RSSI_HI_THRESHOLD 0 RSSILIEN Interrupt Source Enable RSSI Low Enable RSSI low as the source of interrupt which the threshold is set by AM_RSQ_RSSI_LO_THRESHOLD ...

Page 155: ...mmand This property may only be set or read when in powerup mode The default is 0 dB Available in All Default 0x0000 Units dB Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SNRH AM RSQ SNR High Threshold Threshold which triggers the RSQ interrupt if the SNR goes above this threshold ...

Page 156: ...his property may only be set or read when in powerup mode The default is 0 dB Available in All Default 0x0000 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 RSSIH AM RSQ RSSI High Threshold Threshold which triggers the RSQ interrupt if the RSSI goes above this threshold S...

Page 157: ...are set via the AM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MUTE_SNR_THRESHOLD properties The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default slope is 1 dB dB for AMRX component 5 0 or later and 2 dB dB for AMRX component 3 0 or earlier Available in All Default 0x0002 Si4730 31 34 35 36 37 B20 and ea...

Page 158: ...is non zero The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default SNR threshold is 8 dB for AMRX component 5 0 or later and 10 dB for AMRX component 3 0 or earlier Available in All Default 0x000A Si4730 31 34 35 36 37 B20 and earlier Si4740 41 42 43 44 45 C10 and earlier 0x0008 all others Units dB S...

Page 159: ...rup mode The default is 8192 approximately 8000 dB s Release Rate dB s RELEASE 14 0 1 024 Available in Si4740 41 42 43 44 45 Default 0x2000 Range 1 32767 Bit Name Function 15 6 Reserved Always write to 0 5 0 SMTHR AM Soft Mute SNR Threshold The SNR threshold for a tuned frequency below which soft mute is engaged provided the value written to the AM_SOFT_MUTE_MAX_ATTENUATION property is not zero De...

Page 160: ...ault is 8192 approximately 8000 dB s Attack Rate dB s ATTACK 14 0 1 024 Available in Si4740 41 42 43 44 45 Default 0x2000 Range 1 32767 Figure 13 AM Softmute SNR Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 ATTACK 14 0 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SNR dB x 2 y 16 z 10 Default x 4 y 16 z 10 x 2 y 4 z 10 x 2 y 16 z 13 x 0x3301 AM_SOFT_MUTE_SLOPE ...

Page 161: ...208 Available in All Default 0x0208 Units kHz Step 1 kHz Valid Range 149 23000 kHz Recommended Range AM in US 520 1710 kHz AM in Asia 522 1710 kHz SW 2300 23000 kHz LW 153 279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQL 15 0 Bit Name Function 15 0 AMSKFREQL AM Seek Band Bottom Specify the lower boundary of the AM band when performing a seek The seek either stops at...

Page 162: ...ault for AM_SEEK_BAND_TOP After POWER_UP command is complete set AM_SEEK_BAND_TOP to 0x06AE 1710 kHz using the SET_PROPERTY command Units kHz Step 1 kHz Valid Range 149 23000 kHz Recommended Range AM in US 520 1710 kHz AM in Asia 522 1710 kHz SW 2300 23000 kHz LW 153 279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQH 15 0 Bit Name Function 15 0 AMSKFREQH AM Seek Band ...

Page 163: ...t or read when in powerup mode The default frequency spacing is 10 kHz Available in All Default 0x000A Units kHz Valid Values 1 1 kHz 5 5 kHz 9 9 kHz and 10 10 kHz Recommended Value AM in US 10 10 kHz AM in Asia 9 9 kHz SW 5 5 kHz LW 9 9 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 AMSKSPACE 3 0 Bit Name Function 15 4 Reserved Always write to 0 3 0 AMS...

Page 164: ...o send the next command This property may only be set or read when in powerup mode The default is 25 dBµV Available in All Default 0x0019 Units dBµV Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 AMSKSNR 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 AMSKSNR AM Seek Tune SNR Threshold SNR Threshold which determines if a valid channel...

Page 165: ... However to calculate for a different source impedance and or design 1 Drive antenna input with desired source impedance via antenna or antenna dummy 2 Increase RF level until AGC index changes from 19 to 20 Record last RF level with index equal 19 3 Increase RF level until AGC index reaches 39 Record RF level with index equal 39 4 Replace 5600 in rate equation with RF39 RF19 0 00667 Available in ...

Page 166: ... Adjusts the AM AGC for external front end attenuator and external front end cascode LNA This property contains two fields MIN_GAIN_INDEX and ATTN_BACKUP The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0x130C MIN_AGC_INDEX 19 and ATTN_BACKUP 12 Available in Si4740 41 42 43 44 45 Default 0x1...

Page 167: ...g AM_AGC_OVERRIDE command 5 With source impedance in 1 and RF input in 2 adjust attenuator impedance until SINAD requirements are achieved with minimum necessary margin For Si4743EVB Rev 1 3 C7 1200pF attenuates against passive antenna sources and R8 1 ohm attenuates against active 50 ohm sources 6 Enable the AGC using AM_AGC_OVERRIDE 7 Sweep the RF input from 0 to 126 dBuV and then from 126 to 0 ...

Page 168: ...fe to send the next command This property may only be set or read in POWERUP mode The default is 55 µs Available in Si4742 43 44 45 Default 0x0037 Range 15 110 Note Was property 0x4106 in FW2 C Property 0x3902 AM_NB_RATE Noise blanking rate in 100 Hz units The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read in POWERUP mode The de...

Page 169: ...1600 Note Was property 0x4108 in FW2 C Property 0x3904 AM_NB_DELAY Delay in micro seconds before applying impulse blanking to the original samples The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read in POWERUP mode The default is 172 µs Available in Si4742 43 44 45 Default 0x00AC Range 125 219 Note Was property 0x4109 in FW2 C Bi...

Page 170: ...vailable in All Default 0x003F Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 VOL 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 VOL Output Volume Sets the output volume level 63 max 0 min Default is 63 time time time Blanker Input Blanker Output LPF IIR Output AM_NB_DETECT_THRESHOLD AM_NB_INTERVAL AM_NB_RATE sets maximum repeat rate...

Page 171: ...e to send the next command This property may only be set or read when in powerup mode The default is unmute 0x0000 Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LMUTE Mutes both L and R Audio Outputs 0 RMUTE Mutes both L and R Audio Outputs ...

Page 172: ... used for patch file down loads All 0x50 WB_TUNE_FREQ Selects the WB tuning frequency All 0x52 WB_TUNE_STATUS Queries the status of previous WB_TUNE_FREQ or WB_SEEK_START command All 0x53 WB_RSQ_STATUS Queries the status of the Received Signal Quality RSQ of the current channel All 0x54 WB_SAME_STATUS Retrieves Specific Area Message Encoding SAME information and acknowledges SAMEINT interrupts Si4...

Page 173: ... Configures interrupt related to Received Signal Quality metrics 0x0000 All 0x5201 WB_RSQ_SNR_HI_THRESHOLD Sets high threshold for SNR inter rupt 0x007F All 0x5202 WB_RSQ_SNR_LO_THRESHOLD Sets low threshold for SNR inter rupt 0x0000 All 0x5203 WB_RSQ_RSSI_HI_THRESHOLD Sets high threshold for RSSI inter rupt 0x007F All 0x5204 WB_RSQ_RSSI_LO_THRESHOLD Sets low threshold for RSSI inter rupt 0x0000 Al...

Page 174: ...al Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 SAMEINT SAME Interrupt Si4707 Only 0 SAME interrupt has not been triggered 1 SAME interrupt has been triggered 1 ASQINT Audio Signal Quality Interrupt 0 Audio Signal Quality measurement has not been triggered 1 Audio Signal Quality measurement has been trigge...

Page 175: ... configures the state of ROUT pin 13 LOUT pin 14 for analog audio mode For Si4743 component 2A or higher the POWER_UP command also configures the state of GPO3 DCLK pin 19 DFS pin 18 and DOUT pin 17 for digital audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 IRQ is driven high during normal operation and low for a minimum of 1 μs dur...

Page 176: ...llator disabled 1 Use crystal oscillator RCLK and GPO3 DCLK with external 32 768kHz crystal and OPMODE 00000101 See Si47xx Data Sheet Application Schematic for external BOM details 1 3 0 FUNC 3 0 Function 3 WB Receive 0 2 4 14 Reserved 15 Query Library ID 2 7 0 OPMODE 7 0 Application Setting 00000101 Analog audio outputs LOUT ROUT 00001011 Digital audio output DCLK LOUT DFS ROUT DIO 10110000 Digit...

Page 177: ...0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmware Minor Revision ASCII 4 7 0 RESERVED 7 0 Reserved various values 5 7 0 RESERVED 7 0 Reserved various values 6 7 0 CHIPREV 7 0 Chip Revision AS...

Page 178: ...D 0 0 0 1 0 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 PATCHH 7 0 ...

Page 179: ... the pins when in powerdown mode GPIO1 GPIO2 and GPIO3 0 ROUT LOUT DOUT DFS Hiz Available in All Command arguments None Response bytes None Command Response Command 0x12 SET_PROPERTY Sets a property shown in Table 18 WB Receive Property Summary on page 173 The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode Available...

Page 180: ...PL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to modify 4 7 0 PROPVH 7 0 Property Value High Byte This byte in combination with PROPVL is used to set the property value 5 7 0 PROPVL 7 0 Property Value Low Byte This byte in combination with PROPVH is used to set the property value Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 1 1 ARG1 0 0 0 0 0 0 0 0 ARG...

Page 181: ...is command may only be sent when in powerup mode Available in All Command arguments None Response bytes One Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPVH 7 0 RESP3 PROPVL 7 0 RESP Bit Name Function 1 7 0 Reserved Always returns 0 2 7 0 PROPVH 7 0 Property Value High Byte This byte in combination with PROPVL will repr...

Page 182: ...he GET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STC bit if it is already set Available in All Command arguments Three Response bytes None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 0 0 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 Arg Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 FREQH 7 0 Tune Frequency High By...

Page 183: ...d may only be sent when in powerup mode Available in All Command arguments One Response bytes Five Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 INTACK Arg Bit Name Function 1 7 1 Reserved Always write to 0 1 0 INTACK Seek Tune Interrupt Clear If set this bit clears the seek tune complete interrupt status indicator Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X ...

Page 184: ...to send the next command This command may only be sent when in powerup mode Available in All Command arguments One Response bytes Seven Command Data Bit Name Function 1 7 2 Reserved Always returns 0 1 1 AFCRL AFC Rail Indicator This bit will be set if the AFC rails 1 0 VALID Valid Channel Confirms if the tuned channel is currently valid 2 7 0 READFREQH 7 0 Read Frequency High Byte This byte in com...

Page 185: ...hreshold 1 Received SNR has exceeded below SNR low threshold 1 1 RSSIHINT RSSI Detect High 0 RSSI has not exceeded above RSSI high threshold 1 RSSI has exceeded above RSSI high threshold 1 0 RSSILINT RSSI Detect Low 0 RSSI has not exceeded below RSSI low threshold 1 RSSI has exceeded below RSSI low threshold 2 1 AFCRL AFC Rail Indicator This bit will be set if the AFC rails 2 0 VALID Valid Channel...

Page 186: ...mbined with the previously received mes sage to increase the certainty of the message content After receipt of an End of Message this buffer must be cleared by the user To prevent different headers from being combined into an incorrect message the user must clear the buffer before a new header is transmitted As there is no indication that a new header is about to be transmitted the user must rely ...

Page 187: ...nction 1 3 EOMDET End Of Message Detected 1 End of message is detected 1 2 SOMDET Start Of Message Detected 1 start of message is detected 1 1 PREDET Preamble Detected 1 Preamble is detected 1 0 HDRRDY Header Buffer Ready 1 Header buffer is ready 2 7 0 STATE 7 0 State Machine Status 0 End of message 1 Preamble detected 2 Receiving SAME header message 3 SAME header message complete 3 7 0 MSGLEN 7 0...

Page 188: ...presented as a number between 0 low and 3 high 5 3 2 CONF1 1 0 Confidence Metric for DATA1 represented as a number between 0 low and 3 high 5 1 0 CONF0 1 0 Confidence Metric for DATA0 represented as a number between 0 low and 3 high 6 7 0 DATA0 7 0 Byte of message read at address READADDR 0 7 7 0 DATA1 7 0 Byte of message read at address READADDR 1 8 7 0 DATA2 7 0 Byte of message read at address R...

Page 189: ... to send the next command This command may only be sent when in powerup mode Available in All Command arguments One Response bytes Two Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 1 0 1 ARG1 0 0 0 0 0 0 0 INTACK Arg Bit Name Function 1 7 1 Reserved Always write to 0 1 0 INTACK Interrupt Acknowledge 0 Interrupt status preserved 1 Clears ASQINT ALERTOFF_INT ALERTON_INT Bit D7 D6 D5 D4 ...

Page 190: ...st WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK 1 1 0 ALERTON_INT ALERTON_INT 0 1050 Hz alert tone has not been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK 1 1 1050 Hz alert tone has been detected to be present since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK 1 2 0 ALERT ALERT 0 1050 Hz alert tone is currently not present 1 1050 Hz alert tone is currently p...

Page 191: ...ly be sent when in powerup mode Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG Bit Name Function 1 7 1 Reserved Always write to 0 1 0 RFAGCDIS This bit selects whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQIN...

Page 192: ... for high impedance Notes 1 The use of GPO2 as an interrupt pin will override this GPIO_CTL function for GPO2 2 GPO1 is not configurable as an output for Si4740 41 42 43 44 45 Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3O...

Page 193: ... only be set or read when in powerup mode The default is all GPO pins set for high impedance Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level 0 Output low default 1 Output high 1 2 GPO2LEVEL GPO2 ...

Page 194: ...P ASQREP STCREP CTSIEN ERRIEN 0 0 RSQIEN SAMEIEN ASQIEN STCIEN Bit Name Function 15 12 Reserved Always write to 0 11 RSQREP RSQ Interrupt Repeat 0 No interrupt generated when RSQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 SAMEREP SAME Interrupt Repeat Si4707 Only 0 No interrupt generated when SAMEINT is already set default 1 Interrupt generated even if SAMEINT...

Page 195: ...o interrupt generated when ASQINT is set default 1 Interrupt generated when ASQINT is set 0 STCIEN Seek Tune Complete Interrupt Enable 0 No interrupt generated when TCINT is set default 1 Interrupt generated when TCINT is set Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 OFALL OMODE 3 0 OMONO OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 OFALL Digital Output DCLK E...

Page 196: ...o enabling the digital audio output else the device will not respond and will require reset The sample rate must be set to 0 before the DCLK DFS is removed WB_TUNE_FREQ command must be sent after the POWER_UP command to start the internal clocking before setting this property Note DIGITAL_OUPTUT_SAMPLE_RATE is supported in WBRX component 3 0 or later Available in Si4737 39 43 Default 0x0000 digita...

Page 197: ...t be valid 10 ns before and 10 ns after completing the WB_TUNE_FREQ command In addition the RCLK must be valid at all times when the carrier is enabled for proper AGC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode The default is 32768 Hz Available ...

Page 198: ...er times The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode The default is 1 Available in All Default 0x0001 Step 1 Range 1 4095 Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK frequency range is between 31130 and 34406 Hz 32768 5 or 0 to disable AFC Bit D15 D14 D13 D12 D11 ...

Page 199: ...d to Received Signal Quality metrics The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0 Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WBMAXTUNEERR 15 0 Bit Name Function 15 0 WBMAXTUNEERR WB Maximum Tuning Frequency Error Maximum tuning error ...

Page 200: ...HI_THRESHOLD 2 SNRLIEN Interrupt Source Enable Audio SNR Low Enable SNR low as the as the source of interrupt which the threshold is set by WB_RSQ_SNR_LO_THRESHOLD 1 RSSIHIEN Interrupt Source Enable RSSI High Enable RSSI high as the source of interrupt which the threshold is set by WB_RSQ_RSSI_HI_THRESHOLD 0 RSSILIEN Interrupt Source Enable RSSI Low Enable RSSI low as the source of interrupt which...

Page 201: ... is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 127dB Available in All Default 0x007F Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SNRL 15 0 Bit Name Function 15 0 SNRL WB RSQ Audio SNR Low Threshold Threshold which will trigger the RSQ interrupt if the Audio SNR is below this...

Page 202: ...nterrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 3dB Available in All Default 0x0003 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSSIL 15 0 Bit Name Function 15 0 RSSIL WB RSQ RSSI Low Threshold Threshold which will trigger the RSQ interrupt if the RSSI is below this t...

Page 203: ...y may only be set or read when in powerup mode The default is 0 Available in Si4707 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WB_VALID_RSSI_THRESHOLD 15 0 Bit Name Function 15 0 WB_VALID_RSSI_ THRESHOLD WB Valid RSSI Threshold RSSI value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel VALID Specified in units of dB in 1 dB steps 0 12...

Page 204: ...operty may only be set or read when in powerup mode The default is 63 Available in All Default 0x003F Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X X X X X X X X X X X ALERTOFF_IEN ALERTON_IEN Bit Name Function 1 ALERTOFF_IEN Interrupt Source Enable Alert OFF Enable 1050kHz alert tone disappeared as the source of interrupt 0 ALERTON_IEN Interrupt Source E...

Page 205: ...e to send the next command This property may only be set or read when in powerup mode The default is unmute 0x0000 Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LMUTE Mutes both L and R Audio Outputs 0 RMUTE Mutes both L and R Audio Outputs ...

Page 206: ...ed for patch file down loads All 0x61 AUX_ASRC_START Starts sampling rate conversion All 0x65 AUX_ASQ_STATUS Reports audio signal quality metrics All 0x80 GPIO_CNTL Configures GPO1 2 and 3 as output or Hi Z All 0x81 GPIO_SET Sets GPO1 2 and 3 output level low or high All Note Commands PATCH_ARGS and PATCH_DATA are only used to patch firmware For information on applying a patch file see 7 2 Powerup...

Page 207: ... to Send 0 Wait before sending next command 1 Clear to send next command 6 ERR Error 0 No error 1 Error 5 2 Reserved Values may vary 1 ASQINT Audio Signal Quality Interrupt 0 Audio signal quality interrupt has not been triggered 1 Audio signal quality interrupt has been triggered 0 Reserved Values may vary ...

Page 208: ...mand also configures the state of GPO3 DCLK pin 17 DFS pin 14 and DOUT pin 13 for digital audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is complete when the CTS bit and optio...

Page 209: ...ation Setting 01011011 Digital audio outputs DCLK DFS DIO Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X ASQINT X Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X ASQINT X RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number HEX 2 7 0 FWMAJOR 7 0 Firmware ...

Page 210: ...X ASQINT X RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP10 Reserved RESP11 Reserved RESP12 Reserved RESP13 Reserved RESP14 Reserved RESP15 CID 7 0 Si4705 only RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmwar...

Page 211: ...the device does not respond The device will only respond when a POWER_UP command is written GPO pins are powered down and not active during this state For optimal power down current GPO2 must be either internally driven low through GPIO_CTL command or externally driven low Note The following describes the state of all the pins when in powerdown mode GPIO1 GPIO2 and GPIO3 0 DOUT DFS RIN LIN HiZ Ava...

Page 212: ...ve Response bytes None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 0 ARG2 PROPH 7 0 ARG3 PROPL 7 0 ARG4 PROPDH 7 0 ARG5 PROPDL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to modify 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH ...

Page 213: ...ion 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to get 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to get Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X ASQINT X RESP1 0 0 0 0 0 0 0 0 RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0...

Page 214: ...ments None Response bytes None Command Response Command 0x61 AUX_ASRC_START Starts sample rate conversion in signal processing module The CTS bit and optional interrupt is set when it is safe to send the next command The ERR bit and optional interrupt is set if an invalid argument is sent Note that only a single interrupt occurs if both the CTS and ERR bits are set This command may only be sent wh...

Page 215: ... D1 D0 CMD 0 1 1 0 0 1 0 1 ARG1 0 0 0 0 0 0 0 INTACK ARG Bit Name Function 1 0 INTACK Interrupt Acknowledge 0 Interrupt status preserved 1 Clears ASQINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X X ASQINT X RESP1 X X X X X X X OVERLOADINT RESP2 X X X X X X X OVERLOAD RESP3 LEVEL 7 0 RESP Bit Name Function 1 0 OVERLOADINT Audio Signal Overload Interrupt 0 Audio Input Signal overload has not b...

Page 216: ...s set for high impedance Note The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7 4 Reserved Always write...

Page 217: ...erty may only be set or read when in powerup mode The default is all GPO pins set for high impedance Available in All Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level 0 Output low default 1 Output high 1 2 GPO2LEV...

Page 218: ...ilable in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 ASQIEN 0 CTSIEN ERRIEN 0 0 0 0 ASQIEN 0 Bit Name Function 15 10 Reserved Always write to 0 9 ASQREP ASQ Interrupt Repeat 0 No interrupt generated when ASQINT is already set default 1 Interrupt generated even if ASQINT is already set 8 Reserved Always write to 0 7 CTSIEN CTS Interrupt Enable Afte...

Page 219: ...LL OMODE 3 0 OMONO OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 OFALL Digital Output DCLK Edge 0 use DCLK rising edge 1 use DCLK falling edge 6 3 OMODE 3 0 Digital Output Mode 0000 I2 S 0110 Left justified 1000 MSB at second DCLK after DFS pulse 1100 MSB at first DCLK after DFS pulse 2 OMONO Digital Output Mono Mode 0 Use mono stereo blend per blend thresholds 1 Force mono 1 0 OSI...

Page 220: ...ith the sample rate in samples per second The system controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset The sample rate must be set to 0 before the DCLK DFS is removed Available in All Default 0x0000 digital audio output disabled Units sps Range 32 48 ksps 0 to disable digital audio output Bit 15 14 13 12 11 10 ...

Page 221: ...roperty may only be set or read when in powerup mode The default is 32768 Hz The RCLK must be valid 10 ns before sending and 20 ns after completing the AUX_ASRC_START command In addition the RCLK must be valid at all times for proper AFC operation The RCLK may be removed or reconfigured at other times Available in All Default 0x8000 32768 Units 1 Hz Step 1 Hz Range 31130 34406 Table 23 RCLK Gaps P...

Page 222: ...es for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Available in All Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 RCLK SEL REFCLKP 11 0 Bit Name Functi...

Page 223: ...mmand This property may only be set or read when in power up mode The default is 0 Available in All Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0X0000 OVER LOADINT Bit Name Function 15 2 Reserved Always write to 0 1 0 OVERLOADINT Interrupt Source Enable Overload 0 Disable audio signal overload detection interrupt 1 Enable audio signal overload detection interrupt ...

Page 224: ...owerdown mode when the POWER_UP command is written to the command register Once in powerup mode the device accepts additional commands such as tuning and the setting of properties such as power level The device will not accept commands while in powerdown mode with the exception of the powerup command If the system controller writes a command other than POWER_UP when in powerdown mode the device do...

Page 225: ... 8 data bytes in a single 2 wire transaction The first byte is a command and the next seven bytes are arguments Writing more than 8 bytes results in unpredictable device behavior For read operations after the device has acknowledged the control byte it will drive an eight bit data byte on SDIO changing the state of SDIO on the falling edges of SCLK The system controller acknowledges each data byte...

Page 226: ...t the system controller reads the STATUS byte In this example the STATUS byte is 0x00 indicating that the CTS bit bit 8 has not been set The response bytes are not ready for reading and that the device is not ready to accept another command The system controller sets SDIO 1 indicated by NACK 1 to signal to the device the 2 wire transfer will end The system controller should set the STOP condition ...

Page 227: ...K For read operations the control word is followed by a delay of one half SCLK cycle for bus turn around Next the device drives the 16 bit read data word serially on SDIO changing the state of SDIO on each rising edge of SCLK For read operations the control word is followed by a delay of one half SCLK cycle for bus turn around Next the device drives the 16 bit read data word serially on SDIO chang...

Page 228: ...yte stream are not guaranteed to be 0x00 and should be ignored For example GET_PROPERTY has 4 bytes of response data in registers RESPONSE1 RESPONSE2 The contents of registers RESPONSE3 RESPONSE8 are meaningless and not guaranteed to be 0x0000 Likewise for commands which have an odd number of response bytes or a single status byte the least significant byte bits 7 0 of the final register is meanin...

Page 229: ...inal time To read the status and response from the device the system controller sets SEN 0 Next the controller drives the 9 bit control word 101101000b on SDIO consisting of the device address A7 A5 101b the read bit 1b the device address A4 0 and the register address for the STATUS RESPONSE1 register A3 A0 1000b The control word is followed by a 16 bit data word consisting of STATUS followed by R...

Page 230: ...80 read a response device drives one additional byte on SDIO 0xC0 read a response device drives 16 additional bytes on SDIO 0xA0 read a response device drives one additional byte on GPO1 0xE0 read a response device drives 16 additional bytes on GPO1 For write operations the system controller must drive exactly 8 data bytes a command and arguments on SDIO after the control byte The data is captured...

Page 231: ...s not ready to accept another command The system controller sets SEN 1 to end the transfer This process should be repeated until the STATUS byte indicates that CTS bit is set 0x80 in this example When the STATUS byte indicates that the CTS bit has been set 0x80 in this example the system controller may read the response bytes from the device To read the status and response from the device the syst...

Page 232: ...nt from the system controller see Section 7 2 Powerup from a Component Patch After CTS 1 the device is ready to commence normal operation and accept additional commands The POWER_UP command configures the state of DIN pin 13 DFS pin 14 and RIN pin 15 on Si471x 2x and pin 16 on Si4704 05 3x D60 and LIN pin 16 on Si471x 2x and pin 15 on Si4704 05 3x D60 for analog or digital audio modes and GPO2 INT...

Page 233: ... until a CTS interrupt is received if CTS interrupt is enabled 1 Send the POWER_UP command by writing the CMD field with value 0x01 2 Send ARG1 0x01 no patch CTS and GPO2 interrupts disabled AM SW LW receive selected Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument see Section 5 Commands and Properties 3 Send ARG2 0x05 analog output selected 4 Poll th...

Page 234: ...y new component image to allow a customer to test a new component release on their device prior to receiving programmed parts Patches are tagged with a unique identification to allow them to be tracked and are encrypted requiring the customer to use a tag when downloading to allow the Si47xx to decrypt the patch Prior to downloading a partial patch the user must confirm that the device contains th...

Page 235: ...3 1 Table 37 Si4720 21 Firmware Library and Component Compatibility Part Firmware Library FMTX Component FMRX Component Si4720 A10 1 0 R4 2 0 1 0 Si4720 21 B20 2 0 R8 3 0 2 0 Table 38 Si4730 31 Firmware Library and Component Compatibility Part Firmware Library FMRX Component AM_SW_LW RX Component AUXIN Component Si4730 A10 1 0 R4 1 0 1 0 N A Si4730 31 B20 2 0 R9 2 0 2 0 N A Si4730 31 C40 4 0 R10 6...

Page 236: ...6 0 N A Si4734 35 D60 5 0 R11 7 0 6 0 1 0 Table 42 Si4736 37 Firmware Library and Component Compatibility Part Firmware Library FMRX Component AM_SW_LWRX Component WBRX Component Si4736 37 B20 2 0 R9 2 0 2 0 1 0 Si4736 37 C40 4 0 R10 6 0 5 0 5 0 Table 43 Si4738 39 Firmware Library and Component Compatibility Part Firmware Library FMRX Component WBRX Component Si4738 39 B20 2 0 R9 2 0 1 0 Si4738 39...

Page 237: ... download If the checksum fails the part issues an error code ERR bit 6 of the one byte reply that is available after each 8 byte transfer and halts The part must be reset to recover from this error condition The following is an example of a patch file Copyright 2006 Silicon Laboratories Inc Patch generated 21 09 August 09 2006 fmtx version 0 0 alpha 0x15 0x00 0x0B 0x1D 0xBB 0x14 0xC4 0xA1 0x16 0x...

Page 238: ...41 revA Library ID HEX 0x04 library 4 CMD ARG1 ARG2 STATUS 0x01 0xE2 0x50 0x80 POWER_UP Set to FM Transmit set patch enable enable interrupts Set to Analog Line Input Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x15 0x00 0x0B 0x1D 0xBB 0x14 0xC4 0xA1 0x80 Reserved for Patch Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x16 0x98 0x8...

Page 239: ...led for proper AGC operation The RCLK may be removed or reconfigured at other times The RCLK is required for proper AGC operation when the carrier is enabled The RCLK may be removed or reconfigured when the carrier is disabled 3 Write POWER_DOWN to the command register Note that all register contents will be lost 4 Set RST 0 Note that RST must be held high for 10 ns after the completion of the POW...

Page 240: ...ring the digital audio data in DSP mode the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge In all audio formats depending on the word size DCLK frequency and sample rates there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word The number of audio bits can be ...

Page 241: ... the DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE property to 0 After changing or re enabling DCLK DFS user then can set the sample rate property again 5 The property DIGITAL_INPUT_FORMAT and DIGITAL_OUTPUT_FORMAT does not have a condition thus it can be set anywhere after power up Notes 1 Failure to provide DCLK and DFS prior to setting the sample rate property may cause the chip to go...

Page 242: ...TATUS 0x12 0x00 0x01 0x03 or 0x04 0x00 0x00 0x80 SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE Sample rate 0 disable digital audio Reply Status Clear to send high Action User now is allowed to change or disabling DCLK DFS Action DCLK DFS has been changed or re enabled CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x03 or 0x04 0xBB 0x80 0x80 SET_PRO...

Page 243: ... timing model is shown in Figure 28 and the timing parameters for each command are shown in Table 48 Figure 28 CTS Timing Model In addition to CTS bit there are a few commands e g TX_TUNE_FREQ or FM_TUNE_FREQ that use the STC bit to indicate that the command has completed execution It is highly recommended that user waits for the STC bit before sending the next command When interrupt is not used u...

Page 244: ...r the timing is guaranteed and it is called tCOMP The CTS and SET_PROPERTY command completion timing model tCOMP is shown in Figure 30 and the timing parameters for each command are shown in Table 48 Figure 30 CTS and SET_PROPERTY Command Complete tCOMP Timing Model Control Bus COMMAND GPO2 INT tSTC tCTS tINT tINT Control Bus COMMAND GPO2 INT tCOMP tCTS tINT ...

Page 245: ... Command tCTS tSTC tCOMP tINT POWER_UP 110 ms 1 µs POWER_DOWN 300 µs GET_REV GET_PROPERTY GET_INT_STATUS PATCH_ARGS PATCH_DATA TX_ASQ_STATUS TX_RDS_BUFF TX_RDS_PS TX_TUNE_STATUS TX_TUNE_FREQ 100 ms TX_TUNE_MEASURE 100 ms TX_TUNE_POWER 20 ms SET_PROPERTY 10 ms GPIO_CTL GPIO_SET ...

Page 246: ..._SEEK_START 60 ms2 SET_PROPERTY 10 ms FM_AGC_STATUS FM_AGC_OVERRIDE GPIO_CTL GPIO_SET Notes 1 tSTC for FM_TUNE_FREQ FM_SEEK_START commands is 80 ms on FMRX component 2 0 and earlier 2 tSTC is seek time per channel Total seek time depends on bandwidth channel spacing and number of channels to next valid channel Worst case seek time complete for FM_SEEK_START is for USA FM FM_SEEK_BAND_TOP FM_SEEK_B...

Page 247: ...NE_STATUS AM_TUNE_FREQ 80 ms AM_SEEK_START 80 ms SET_PROPERTY 10 ms GPIO_CTL GPIO_SET Note tSTC is seek time per channel The worst case seek time per channel is 200 ms Total seek time depends on bandwidth channel spacing and number of channels to next valid channel Worst case seek time complete for AM_SEEK_START is for USA AM AM_SEEK_BAND_TOP AM_SEEK_BAND_BOTTOM AM_SEEK_FREQ_SPACING 1 tSTC 1710 52...

Page 248: ...TCH_ARGS PATCH_DATA WB_RSQ_STATUS WB_ASQ_STATUS WB_TUNE_STATUS WB_TUNE_FREQ 250 ms SET_PROPERTY 10 ms WB_AGC_STATUS WB_AGC_OVERRIDE GPIO_CTL GPIO_SET Table 52 Command Timing Parameters for the Stereo Audio ADC Mode Command tCTS tCOMP tINT POWER_UP 110 ms 1 µs POWER_DOWN 300 µs GET_REV GET_PROPERTY GET_INT_STATUS AUX_ASRC_START AUX_ASQ_STATUS GPIO_CTL GPIO_SET SET_PROPERTY 10 ms ...

Page 249: ...compressed by a 2 to 1 dB ratio meaning that every 2 dB increase in audio input level above the threshold results in an audio output increase of 1 dB In this example the input dynamic range of 90 dB is reduced to an output dynamic range of 70 dB The FM Transmitter includes digital audio dynamic range control with programmable gain threshold attack rate and release rate The total dynamic range redu...

Page 250: ...response Depending on the region a time constant of either 50 or 75 µs is used The frequency response of both of these filters is shown in Figure 33 For a 75 µs filter a 15 kHz tone is amplified by 17 dB For a 50 µs filter a 15 kHz tone is amplified by 13 5 dB The pre emphasis time constant is programmable to off 50 or 75 µs and is setting the TX_PREEMPHASIS property When using the pre emphasis fi...

Page 251: ...mizing Audio Volume for FM Transmitter The audio input chain is shown in Figure 34 Figure 34 Audio Input Chain To maximize audio volume 1 Set the input line attenuation line level and audio deviation The input line attenuation should be set to the lowest setting that is above the maximum level provided by the audio source either 190 301 416 or 636 mVPK The line level should be set to the maximum s...

Page 252: ...resistance of 60 k An external series resistor on LIN and RIN inputs of 58 k would create a resistive voltage divider that would keep the maximum line level on RIN LIN below 509 mVPK to give a 2 dB headroom With input signal at 509 mVPK 75 µs pre emphasis and the limiter enabled the Line Level can be set to 636 mVPK 2 Enable the audio dynamic range control In general the greater the sum of thresho...

Page 253: ... Programming Example for the FM RDS Transmitter The following flowchart is an overview of how to program the FM RDS transmitter RESET CHIP STATE POWER DOWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP with GPO2OEN bit enabled command 0x01 Library ID Compatible w patch POWER_UP with Patch and GPO2OEN bits enabled command 0x01 Send Patch D...

Page 254: ...ttings property 0x0201 0x0202 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Call TX_TUNE_STATUS with INTACK bit set command 0x33 Set Transmit Power command 0x31 Use GET_INT_STATUS command 0x14 or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set command 0x33 ...

Page 255: ... Stereo components property 0x2100 Stereo Mono Disable RDS components property 0x2100 Set RDS Deviation property 0x2103 Enable RDS components property 0x2100 Set RDS properties property 0x2C00 0x2C07 Send RDS PS Group Type0 command 0x36 Send any other RDS Group Type 1 15 Send RDS Group Type 1 15 command 0x35 Yes No Yes No Set Audio Deviation property 0x2101 ...

Page 256: ...roperty 0x2200 05 Disable Limiter property 0x2200 Yes No Set FM Transmit Frequency command 0x30 Set Transmit Power command 0x31 CHIP STATE TRANSMITTING Query TX_TUNE_STATUS command 0x33 Use GET_INT_STATUS command 0x14 or hardware interrupts until STC bit is set Call TX_TUNE_STATUS with INTACK bit set command 0x33 Use GET_INT_STATUS command 0x14 or hardware interrupts until STC bit is set Call TX_T...

Page 257: ...Send TX_TUNE_MEASURE command 0x32 Do host processing On returned RPS value To find empty channels CHIP STATE Received Idle Set FM Transmit Freq and or Power CHIP STATE TRANSMITTING Yes No Yes No LOOP from start_freq to end_freq until DONE Analog Digital Audio Input Set ANALOG input settings 0x2104 Digital Analog Enable digital audio by setting DFS sample rate property 0x0103 Clock must be availabl...

Page 258: ...erties on page 7 for a full description of each command and property Note If hardware interrupts are required the GPO2OEN flag 0x40 ARG1 must be set in the POWER_UP command Change Chip Function To FM Receive Si472x only Send POWER_DOWN command 0x11 Yes CHIP STATE POWER DOWN Send POWER_UP For FM Receive command 0x01 CHIP STATE POWER UP FM Receive Look at FM Receive Flowchart No TRANSMISSION DONE Ye...

Page 259: ... Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x04 0x21 0x5E 0x80 SET_PROPERTY TX_LINE_INPUT_LEVEL Input Range 419mVPK 74kΩ Max peak input level 350mVPK 0x15E Reply Status Clear to send high Configuration CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 0x10 0x00 0x80 0x0D 0x32 0x30 0xE4 0xD6 0x32 0x30 0x41 GET_REV Reply Status C...

Page 260: ...T_LEVEL_MUTE Sets Left and Right channel mute Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x06 0x00 0x01 0x80 SET_PROPERTY TX_PREEMPHASIS 50 µs Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x07 0x4A 0x38 0x80 SET_PROPERTY TX_PILOT_FREQUENCY Sets the pilot or tone generator frequ...

Page 261: ...gh STCINT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x73 0xAB 0x00 TX_TUNE_STATUS Clear STC interrupt Reply Status Clear to send high Frequency 0x277E 10110d 101 1 MHz Transmit voltage 0x73 115d 115 dBµV Tuning capacitor 191 range 0 191 Received noise level 0x00 CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x00 0x00 0...

Page 262: ...OPD ARG5 PROPD STATUS 0x12 0x00 0x22 0x01 0xFF 0xD8 0x80 SET_PROPERTY TX_ACOMP_THRESHOLD Threshold 40 dBFS 0xFFD8 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x22 0x04 0x00 0x0F 0x80 SET_PROPERTY TX_ACOMP_GAIN Gain 15 dB 0xF Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x22 0x03 0x00 0x04...

Page 263: ...00 0xCE 0x80 SET_PROPERTY TX_ASQ_LOW_LEVEL 50 dB 0x00CE Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x23 0x02 0x27 0x10 0x80 SET_PROPERTY TX_ASQ_DURATION_LOW 10000 ms 0x2710 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x23 0x03 0x00 0xEC 0x80 SET_PROPERTY TX_ASQ_HIGH_LEVEL 20 dB 0x00EC R...

Page 264: ...0 21 Only CMD ARG1 ARG2 ARG3 ARG4 STATUS 0x32 0x00 0x27 0x7E 0x00 0x80 TX_TUNE_MEASURE Set frequency to 101 1 MHz 10110d 0x277E Set antenna tuning capacitor to auto Reply Status Clear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply Status Clear to send high STCINT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x00 0xAB 0x32 TX_TUNE_STATUS Cle...

Page 265: ... PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x01 0x19 0xE1 0x80 SET_PROPERTY TX_AUDIO_DEVIATION 66 25 kHz 6625d 0x19E1 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x03 0x00 0xC8 0x80 SET_PROPERTY TX_RDS_DEVIATION Si4711 13 21 Only 2 kHz 200d 0xC8 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0...

Page 266: ...y Sets program service repeat count to 3 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x2C 0x05 0x00 0x03 0x80 SET PROPERTY TX_RDS_PS_MESSAGE_COUNT Si4711 13 21 Only Sets PS message count to 3 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x2C 0x06 0xE1 0x02 0x80 SET_PROPERTY TX_RDS_PS_AF S...

Page 267: ...te text is SILABS SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS 0x36 0x03 0x31 0x58 0x20 0x20 0x80 TX_RDS_PS Si4711 13 21 Only PSID 3 Set text 1X Complete text is SILABS SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS 0x36 0x04 0x52 0x44 0x53 0x20 0x80 TX_RDS_PS Si4711 13 21 Only PSID 4 Set text RDS Complete text is SILABS S...

Page 268: ... 0x02 0x4C 0x41 0x42 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 2 Set text LABO Complete text is SILICON LABORATORIES SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x35 0x04 0x20 0x03 0x52 0x41 0x54 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 3 Set text RATO Complete text is SILICON...

Page 269: ...x20 0x07 0x52 0x44 0x53 0x20 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 7 Set text RDS Complete text is SILICON LABORATORIES SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x35 0x04 0x20 0x08 0x44 0x45 0x4D 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 8 Set text DEMO Complete text is SILIC...

Page 270: ...ar the STC bit after it has been set CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x00 0x00 0x07 0x80 SET_PROPERTY TX_COMPONENT_ENABLE Si4711 13 21 Only Enable Stereo LMR Pilot and RDS Reply Status Clear to send high CMD STATUS 0x14 0x84 GET_INT_STATUS Reply Status Clear to send high RDSINT 1 CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 0x...

Page 271: ... Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP with GPO2OEN bit enabled command 0x01 Library ID Compatible w patch POWER_UP with Patch and GPO2OEN bits enabled command 0x01 Send Patch Data command 0x15 0x16 Yes No Yes No Check Chip FW Comp rev GET_REV command 0x10 Chip FW Comp Rev are correct Contact Silabs For verification No Yes Contact Silabs For verifica...

Page 272: ...nna Si4706 only Set FM_ANTENNA_INPUT property 0x1107 1 Set FM_ANTENNA_INPUT property 0x1107 0 LPI pin for embedded short antenna FMI pin for headphone long antenna Use GET_INT_STATUS command 0x14 or hardware interrupts Until STC bit is set Call FM_TUNE_STATUS With INTACK bit set command 0x22 Digital output mode Si4706 41 43 45 only Enable digital audio by setting DFS sample rate property 0x0104 Ye...

Page 273: ... t F M T u n e F re q u e n c y c o m m a n d 0 x 2 0 C H IP S T A T E R E C E IV IN G F M Q u e ry F M _ T U N E _ S T A T U S c o m m a n d 0 x 2 2 S e t V o lu m e p ro p e rty 0 x 4 0 0 0 S e t M u te U n m u te p ro p e rty 0 x 4 0 0 1 N o t a p p lic a b le to S i4 7 4 9 U s e G E T _ IN T _ S T A T U S c o m m a n d 0 x 1 4 o r h a rd w a re in te rru p ts U n til S T C b it is s e t C a ll...

Page 274: ... FM_RDS_INT_FIFO_COUNT property 0x1501 Set FM_RDS_CONFIG enable RDS property 0x1502 Yes Read RDS data with FM_RDS_STATUS command 0x24 Received RDS Interrupt or poll RDSINT from GET_INT_STATUS LOOP until RDS FIFO is empty Process RDS data on the host Disable RDS in FM_RDS_CONFIG property 0x1502 No ...

Page 275: ...s N o S e t S E E K se ttin g s p ro p e rty 0 x1 4 00 1 4 0 4 S E E K n e xt V a lid ch a n n e l S e t S E E K se ttin g s p ro p e rty 0 x1 4 0 0 1 4 0 4 S e n d F M _ S E E K _ S T A R T co m m a n d 0 x 21 Y e s C H IP S T A T E R E C E IV IN G F M N o L O O P u n til rea ch es e n d of F M b a nd o r b ack to th e o rigin a l C h a n n e l S e n d F M _S E E K _ S T A R T co m m a n d 0 x2 1...

Page 276: ...e Or WB Receive Flowchart No RECEIVE FM DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in FM Receive Need to change DCLK DFS Rate digital only Disable digital audio by setting DFS sample rate to 0 property 0x0104 Change DCLK DFS rate or Disabl...

Page 277: ...nsure that DCLK and DFS are already supplied CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_RATE Sample rate 48000Hz 0xBB80 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x02 0x00 0x00 0x80 SET_PROPERTY DIGITAL_OUTPUT_FORMAT Mode I2S stereo 16bit sample on ris...

Page 278: ...ESCALE Divide by 400 example RCLK 13 MHz REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x40 0x00 0x00 0x3F 0x80 SET_PROPERTY RX_VOLUME Output Volume 63 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x11 0x00 0x00 0x01 0x80 SET_PROPERTY FM_DEEMPHASIS 50 µs Reply Status Clear t...

Page 279: ...0 kHz 0x0028 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x12 0x00 0x00 0x8F 0x80 SET_PROPERTY FM_RSQ_INT_SOURCE Enable blend SNR high SNR low RSSI high and RSSI low interrupts Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x12 0x01 0x00 0x1E 0x80 SET_PROPERTY FM_RSQ_SNR_HI_THRESHOLD Thres...

Page 280: ...ESHOLD Pilot 1 Threshold 50 0x0032 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x13 0x02 0x00 0x0A 0x80 SET_PROPERTY FM_SOFT_MUTE_MAX_ATTENUATION Attenuation 10 dB 0x000A Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x13 0x03 0x00 0x06 0x80 SET_PROPERTY FM_SOFT_MUTE_SNR_THRESHOLD Threshol...

Page 281: ... ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x14 0x04 0x00 0x14 0x80 SET_PROPERTY FM_SEEK_TUNE_RSSI_THRESHOLD Threshold 20 dBµV 0x0014 Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 STATUS 0x20 0x00 0x27 0xF6 0x00 0x80 FM_TUNE_FREQ Set frequency to 102 3 MHz 0x27F6 Set antenna tuning capacitor to auto Reply Status Clear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply Status C...

Page 282: ... 0x2C 0x00 0x00 FM_TUNE_STATUS Clear STC interrupt Reply Status Clear to send high Valid Frequency Frequency 0x286E 103 5 MHz RSSI 34 dBµV SNR 44 dB Antenna tuning capacitor 0 range 0 191 RDS Si4706 41 43 45 49 Only CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x15 0x00 0x00 0x01 0x80 SET_PROPERTY FM_RDS_INT_SOURCE Enable RDSRECV interrupt set RDSINT bit when RDS has filled ...

Page 283: ... Block A 0x40A7 PI Code 0x40A7 KSLB Block B 0x2000 Group Type 2A Radio Text RT PTY 00000b Undefined Address code 0000b 0 char 1 2 3 4 Block C 0x5349 SI Block D 0x4C49 LI BLE 0 No Error Current RT SILI CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x16 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x53 0x49 0x00 FM_RDS_STATUS Clear RDS interrupt...

Page 284: ... No Error Current RT SILICON CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x15 0x40 0xA7 0x00 0x09 0xE1 0x02 0x4C 0x41 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x15 21 FIFO receives another ...

Page 285: ...o Error Current RT SILICON LABO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x14 0x40 0xA7 0x00 0x0A 0xE1 0x02 0x42 0x53 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x14 20 FIFO receives anoth...

Page 286: ...o Error Current RT SILICON LABORATO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x13 0x40 0xA7 0x00 0x0B 0xE1 0x02 0x20 0x20 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x13 19 FIFO receives a...

Page 287: ...No Error Current RT SILICON LABORATORIES CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x12 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x52 0x44 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x12 18 FIFO recei...

Page 288: ...x4934 I4 BLE 0 No Error Current RT SILICON LABORATORIES SI4 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x10 0x40 0xA7 0x00 0x09 0xE1 0x02 0x53 0x20 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used...

Page 289: ...5820 x BLE 0 No Error Current RT SILICON LABORATORIES SI471x CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0E 0x40 0xA7 0x00 0x0A 0xE1 0x02 0x44 0x45 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Use...

Page 290: ...x5244 RD Block D 0x5320 S BLE 0 No Error Current RT SILICON LABORATORIES SI471x RDS CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x00 0x0B 0xE1 0x02 0x4D 0x4F 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No...

Page 291: ...45 DE Block D 0x4D4F MO BLE 0 No Error Current RT SILICON LABORATORIES SI471x RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0C 0x40 0xA7 0x00 0x0C 0xE1 0x02 0x53 0x49 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized...

Page 292: ... STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x20 0x09 0x0D 0x00 0x00 0x00 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x0C 12 FIFO receives another group while querying Block A 0x40A7 P...

Page 293: ...ower Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP with GPO2OEN bit enabled command 0x01 Library ID Compatible w patch POWER_UP with Patch and GPO2OEN bits enabled command 0x01 Send Patch Data command 0x15 0x16 Yes No Yes No Check Chip FW Comp rev GET_REV command 0x10 Chip FW Comp Rev are correct Contact Silabs For verification No Yes Contact Silabs For verificati...

Page 294: ...s property 0x0201 0x0202 Set DIGITAL output settings property 0x0102 0x0104 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Yes No Use GET_INT_STATUS command 0x14 or hardware interrupts Until STC bit is set Call AM_TUNE_STATUS With INTACK bit set command 0x42 ...

Page 295: ...E IV IN G A M S W L W Q u e ry A M _ T U N E _ S T A T U S c o m m a n d 0 x 4 2 S e t V o lu m e p ro p e rty 0 x 4 0 0 0 S e t M u te U n m u te p ro p e rty 0 x 4 0 0 1 S e t A M T u n e F re q u e n c y c o m m a n d 0 x 4 0 U s e G E T _ IN T _ S T A T U S c o m m a n d 0 x 1 4 o r h a rd w a re in te rru p ts U n til S T C b it is s e t C a ll A M _ T U N E _ S T A T U S W ith IN T A C K b i...

Page 296: ...t Yes No Yes No LOOP until reaches end of AM band or back to the original channel SEEK next Valid channel Set SEEK settings property 0x3400 3404 SEND AM_SEEK_START COMMAND 0X41 Yes No Set SEEK settings property 0x3400 3404 Send AM_SEEK_START command 0X41 CHIP STATE RECEIVING AM SW LW CHIP STATE RECEIVING AM SW LW Use GET_INT_STATUS command 0x14 or hardware interrupts until STC bit is set Call AM_T...

Page 297: ...ather Band command 0x01 CHIP STATE POWER UP FM Receive or Weather Band Look at FM Receive or Weather Band Flowchart No RECEIVE AM SW LW DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in AM SW LW Receive ...

Page 298: ...SW Receiver Action Data Description Powerup in Digital Mode CMD ARG1 ARG2 STATUS 0x01 0xC1 0xB0 0x80 POWER_UP Set to AM LW SW Receive Enable interrupts Set to Digital Audio Output Reply Status Clear to send high Action Ensure that DCLK and DFS are already supplied CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_RATE Sa...

Page 299: ...CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 SET_PROPERTY REFCLK_FREQ REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x02 0x01 0x90 0x80 SET_PROPERTY REFCLK_PRESCALE Divide by 400 example RCLK 13 MHz REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP A...

Page 300: ... AM_RSQ_SNR_HIGH_THRESHOLD 10 dB 0x0A Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x32 0x02 0x00 0x0A 0x80 SET_PROPERTY AM_RSQ_SNR_LOW_THRESHOLD 10 dB 0x0A Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x32 0x03 0x00 0x1E 0x80 SET_PROPERTY AM_RSQ_RSSI_HIGH_THRESHOLD 30 dBµV 0x1E Reply Stat...

Page 301: ...PROPERTY AM_SEEK_BAND_BOTTOM 520 kHz 0x0208 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x34 0x01 0x06 0xAE 0x80 SET_PROPERTY AM_SEEK_BAND_TOP 1710 kHz 0x06AE Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x34 0x02 0x00 0x0A 0x80 SET_PROPERTY AM_SEEK_FREQ_SPACING 10 kHz 0x000A Reply Status...

Page 302: ...INT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x42 0x01 0x80 0x01 0x03 0xE8 0x2A 0x1A 0x0D 0x95 AM_TUNE_STATUS Clear STC interrupt Reply Status Clear to send high Channel is valid AFC is not railed and seek did not wrap at AM band boundary Frequency 0x03E8 1000 kHz RSSI 0x2A 42d 42 dBµV SNR 0x1A 26d 26 dB Value the antenna tuning capacitor is set to 0x0D95 3477 dec CMD ARG1 STATU...

Page 303: ...or the STC bit to be set prior to performing other commands Use AM_TUNE_STATUS to clear the STC bit after it has been set 12 4 Programming Example for the WB SAME Receiver The following flowchart is an overview of how to program the WB Weather Band Receiver RESET CHIP STATE POWER DOWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP with GPO...

Page 304: ...settings property 0x0201 0x0202 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Use GET_INT_STATUS command 0x14 or hardware interrupts until STC bit is set Call WB_TUNE_STATUS with INTACK bit set command 0x52 ...

Page 305: ... 2 S e t V o lu m e p ro p e rty 0 x 4 0 0 0 S e t M u te U n m u te p ro p e rty 0 x 4 0 0 1 S e t W B V a lid S N R T h re s h o ld p ro p e rty 0 x 5 4 0 3 S e t W B V a lid R S S I T h re s h o ld p ro p e rty 0 x 5 4 0 4 U s e G E T _ IN T _ S T A T U S c o m m a n d 0 x 1 4 o r h a rd w a re in te rru p ts u n til S T C b it is s e t C a ll W B _ T U N E _ S T A T U S w ith IN T A C K b it s...

Page 306: ...hing based on WB_RSQ_STATUS Yes No Monitor Alert Tone ASQ Set ASQ int source property 0x5600 Query WB_ASQ_STATUS command 0x55 Optional Do something based on WB_ASQ_STATUS Yes No Monitor SAME Set SAME int source property 0x5500 Query WB_SAME_STATUS command 0x54 Optional Do something based on WB_SAME_STATUS Yes No Comlete Message Received No Yes ...

Page 307: ...r FM Receive command 0x01 CHIP STATE POWER UP AM or FM Receive Look at AM or FM Receive Flowchart No RECEIVE WB DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in WB Receive ...

Page 308: ...PT Source 0x0B Tune to WB Channel WB_TUNE_FREQ Disable Timer Set HDR_COUNT 0 Check Interrupt Status GET_INT_STATUS SAME_INT or ASQ_INT 1 TIMER 6 SEC Clear SAME buffer Disable timer and SET_HDR COUNT 0 INT TYPE Call WB_SAME_STATUS INT_ACK 1 EOM_DET 1 PRE_DET 1 HDR_RDY 1 at this point Increment HDR_COUNT Get Message and Process WB_SAME_STATUS HDR_COUNT 3 Reset Timer Yes No Yes Yes Yes No Yes No No N...

Page 309: ... POWER_UP Set to weatherband receive Enable interrupts Set to Analog Out Reply Status Clear to send high CMD STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 0x10 0x80 0x25 0x30 0x41 0x13 0x36 0x30 0x41 0x42 GET_REV Reply Status Clear to send high Part Number HEX 0x25 37 dec Si4737 Firmware Major Rev ASCII 0x30 0 Firmware Minor Rev ASCII 0x41 A Patch ID MSB example only Patch ID LSB example ...

Page 310: ...PD ARG5 PROPD STATUS 0x12 0x00 0x54 0x04 0x00 0x14 0x80 SET_PROPERTY WB_VALID_RSSI_THRESHOLD Threshold 20 dBµV 0x0014 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x56 0x00 0x00 0x01 0x80 SET_PROPERTY WB_ASQ_INTERRUPT_SOURCE Interrupt when alert tone is present Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD ...

Page 311: ... Valid Frequency Frequency 0xFDC0 162 4 MHz RSSI 34 dBµV SNR 23 dB CMD ARG1 STATUS RESP1 0x55 0x01 0x80 0x02 WB_ASQ_STATUS Reply Status Clear to send high Alert tone is not present SAME Si4707 Only CMD STATUS 0x14 0x84 GET_INT_STATUS Reply Status Clear to send high SAMEINT 1 CMD ARG1 ARG2 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x54 0x01 0x00 0x80 0x0F 0x0...

Page 312: ... B20 Si4730 B20 GM GU AM FM Receiver B 20 B20 Si4731 B20 GM GU AM FM RDS Receiver B 20 B20 Si4734 B20 GM GU AM SW FM Receiver B 20 B20 Si4735 B20 GM GU AM SW FM RDS Receiver B 20 B20 Si4704 C40 GM GU FM Receiver C 40 C40 Si4705 C40 GM GU FM RDS Receiver C 40 C40 Si4730 C40 GM GU AM FM Receiver C 40 C40 Si4731 C40 GM GU AM FM RDS Receiver C 40 C40 Si4734 C40 GM GU AM SW FM Receiver C 40 C40 Si4735 ...

Page 313: ...onfiguration 0x120x Properties FM_RSQ_MULTIPATH_HIGH_THRESHOLD 0x1205 127 D60 FM_RSQ_MULTIPATH_LOW_THRESHOLD 0x1206 0 D60 Properties 0x1205 and 0x1206 are only available on D60 parts FM Soft Mute Configuration 0x130x Properties FM_SOFT_MUTE_SLOPE 0x1301 2 C40 D60 The target soft mute target attenuation up to a set maximum attenuation level is calculated as the difference between the soft mute thre...

Page 314: ... thresholds For each set of thresholds separate blend attack into mono and release into stereo rates may be set Each of the factors is independently evaluated and any may trigger a blend into mono at its given threshold and rate To remove any of the advanced blend factors from consideration set the corresponding blend thresholds to min value of 0 for SNR based blend 0x1804 0x1805 and set the corre...

Page 315: ...SOFT_MUTE_SLOPE 0x3301 2 B20 1 C40 D60 AM_SOFT_MUTE_MAX_ATTENUATION 0x3302 16 B20 8 C40 D60 AM_SOFT_MUTE_SNR_THRESHOLD 0x3303 10 B20 8 C40 D60 Settings for Audio Soft Mute Soft mute is active when SNR falls below the given AM_SOFT_MUTE_SNR_THRESHOLD When active the output audio will be decreased at a set rate until the target soft mute attenuation is achieved In B20 devices the threshold is 10 dB ...

Page 316: ...Revision Firmware Revision Suffix Si4704 B20 GM GU FM Receiver B 20 B20 Si4705 B20 GM GU FM RDS Receiver B 20 B20 Si4730 B20 GM GU AM FM Receiver B 20 B20 Si4731 B20 GM GU AM FM RDS Receiver B 20 B20 Si4734 B20 GM GU AM SW FM Receiver B 20 B20 Si4735 B20 GM GU AM SW FM RDS Receiver B 20 B20 Si4704 C40 GM GU FM Receiver C 40 C40 Si4705 C40 GM GU FM RDS Receiver C 40 C40 Si4730 C40 GM GU AM FM Recei...

Page 317: ...LD property 0x1809 to 100 0x64 AM Receive Mode Si473x D60 devices are compatible with Si473x C40 devices in AMRX mode WB Receive Mode There are no Si473x D60 devices which support WBRX mode To Achieve Similar Performance in SI4704 05 3X D60 to SI4704 05 3X B20 The D60 devices have a more advanced feature set than B20 devices This section describes a step by step procedure to achieve similar perfor...

Page 318: ...to Si4704 05 3X B20 This section describes a step by step procedure to achieve performance from C40 devices that is similar to that of B20 devices FM Receiver Mode Si473x C40 devices are compatible with Si473x B20 devices in FMRX mode AM Receive Mode Set the AM_MODE_AVC_MAX_GAIN property 0x3103 to 0x7800 maximum Set the AM_SOFT_MUTE_THRESHOLD property 0x3303 to 10 db Set the AM_SOFT_MUTE_SLOPE pro...

Page 319: ...product matrix in Table 1 Revision 0 3 to Revision 0 4 Added Si4704 05 30 31 34 35 36 37 38 39 C40 receiver support and additional AM properties Added Si4784 85 B20 receiver support Updated product matrix in Table 1 Updated with corrections to couple commands and properties Revision 0 4 to Revision 0 41 Minor edits Revision 0 41 to Revision 0 5 Combined information in AN332 Rev 0 41 and AN344 Rev ...

Page 320: ...oning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaim...

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