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1/27/15

SigC667x / SigC641x User Guide, Rev B7

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Signalogic 2012-2014

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5 pn4Test Host Program

Note

This section only applies to SigC641x DSP systems.

The pn4Test host program controls and tests the McBSP1 and GPIO devices on the selected
DSPs. During pn4Test operation, data is transmitted and received between selected DSPs, and
real-time results are displayed in a Linux terminal window.

To build pn4Test, enter:

#cd .. /SigC641x/apps/SigC64x/pn4Test

#make

Running pn4Test with the command

./pn4Test –h

will list the available command line options noting which options are mandatory for running
pn4Test with a “+” sign. Supported command line options are listed below:

-d<0…2>

0 – Detail display is disabled.

1 – Probe counters for each time the specified ISR (GPIO, TX, or RX) is entered

are displayed on each display updated.

2 – FPGA revision numbers and memory symbol addresses are displayed once.

Sync data for MCBSP and MCBSP_GPIO test modes is displayed once. A

message indicating a signal was received with the DSP number that HINT was

generated on is displayed each time the signal handler runs.

-f<N>

Sets the processor clock rate in MHz. (e.g.

–f720

or

-f1000

)

-m<bitmask>

Sets the processor select bit mask. Values can be entered in decimal or hex
(e.g.

–m17

is equivalent to

–m0x11

). Only one DSP from group A (DSPs

0-3) and only one DSP from group B (DSPs 4-7) should be selected for
testing. If other settings are used, the first DSP from each group will be
used, but the data display may not reflect the desired testing mode.

-e<DSP COFF file name>

(e.g.

-etmsc64xx_rtaf_ccs3.out

)

-c<designator>

Sets card designator (e.g.

-cSIGC64XX

)

-M<Test Mode>

Available options are listed below

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Summary of Contents for SigC641x

Page 1: ...2014 Signalogic Inc Revision B8 January 2015 Signalogic Inc 9617 Wendell Skillman Dallas TX 75243 Tel 214 349 5551 Fax 214 343 0163 http www signalogic com tech_support signalogic com 1 Includes SigC667x 32 core and 64 core PCIe cards and SigC641x PCI PCIe cards and PTMC modules 2 Includes Texas Instruments code gen tools installation ...

Page 2: ...xternal Power Cables 20 4 Software Installation 23 4 1 Building the Loadable Kernel Module LKM Driver 27 4 1 1 Linux Kernel Devel Installation Requirement 29 4 2 Building DirectCore Libraries 31 4 3 Test Programs 34 4 3 1 memTest 35 4 3 2 boardTest 42 4 3 3 fftTest 45 4 3 4 videoTest 48 4 3 5 appTest 51 4 3 5 1 appTest Output Description 52 4 3 5 2 RTP Audio Test Program 54 4 3 5 2 1 Installing an...

Page 3: ...F Development and Host Platform Notes 88 4 5 3 1 Linux Platform Builds 90 4 6 CIM Software Installation 92 4 6 1 Running User Programs with CIM 92 4 6 2 h264_encode demo 93 5 pn4Test Host Program 98 6 pn4Test Theory of Operation 104 6 1 MCBSP Test Mode 107 6 2 UART Test Mode 107 6 3 GPIO Test Mode 108 6 4 Host Operation 109 ...

Page 4: ...n and software changes Modified Rev B4 Mar 2013 added video encoding test sections Modified Rev B5 Jun 2013 added RTAF software usage section updated memTest Modified Rev B6 Aug 2013 added apptest and call test procedures Modified Rev B7 Nov 2014 added fftTest and videoTest DirectCore demo program sections CIM software install and build details and CIM h264_encode demo section Modified Rev B8 Jan ...

Page 5: ...SigC667x Card Overview The SigC6678 32 and SigC6678 64 are 32 core and 64 core Gen2 and Gen3 PCIe cards respectively These cards combine CIM Compute Intensive Multicore cores with high bandwidth PCIe interface and large amounts of memory per core both shared between cores and dedicated external core memory From the top of the card the CIM devices can be seen as shown in Figures 1 1a and 1 1b below...

Page 6: ...e host server Additional airflow from the server is typically not required due to the self contained heat sink and fan Maximum power consumption is about 54W for the 32 core card and about 110W for the 64 core card CAUTION Power should be fully removed from the motherboard prior to card installation Be sure that the card is correctly justified in the slot the backplate on the card is not obstructe...

Page 7: ...TION It is a known issue that in some servers SigC667x cards with A101 revision firmware may not complete their on card I2C boot process before the server completes its internal BIOS scan of the PCIe device tree which includes PCIe slots There are four 4 PCIe LEDs on the SigC667x card that will flash to indicate valid PCIe initialization after boot The placement of these LEDs is shown in Figures 1...

Page 8: ... 4 PCIe boot LEDs top side Figure 1 5 PCIe boot LEDs bottom side If after boot all PCIe LEDs are not flashing then a system reset either through software for example shutdown r now Linux command or front panel switch can be performed This is not an issue on cards with A102 revision firmware ...

Page 9: ...of the card near the inner edge of the PCIe connector as shown in Figure 1 6 below Figure 1 6 SigC6678 32 card and firmware revision information For SigC6678 64 cards card and firmware revision information is printed on the back side of the card as shown in Figure 1 7 below Figure 1 7 SigC6678 64 card and firmware revision information Card revision information is given in the Table 1 1 below ...

Page 10: ...2014 10 109 Hardware Version Table Card Type Revision Silkscreen labeling on back of card SigC6678 32 SigC6678 64 9692868100E or 9692868100 A101 9692868101E A102 9692868102E A103 19C2868200 A101 19C2868201 01 A102 Table 1 1 SigC667x card and firmware revision information ...

Page 11: ...nd a PCI interface From the top of the card two C6415T devices can be seen as shown in Figure 2 1 below Figure 2 1 Top view of SigC6415T PMC module From the bottom of the card the remaining six C6415T devices PCI interface logic FPGA PN4 interface logic FPGA and PMC interface connectors can be seen The PN4 connector is at the upper right as shown in Figure 2 2 Figure 2 2 Bottom view of SIGC6415T P...

Page 12: ...in Figure 2 4 Ensure that a complete connection is made on the PMC interface when inserting the module press firmly but gently and press at the edges of the module i e not directly on components After insertion check carefully for any gaps around the edges of all four 4 PMC connectors Also make sure the module rests completely flat and in parallel with the adapter card and the module s front bezel...

Page 13: ...el plate should be on the edge of the motherboard with the 4 wire internal power connector towards the interior The card installed into a PCI express slot using a Dynamic Engineering adapter is shown in Figure 2 5 In the case of using a PCI X adapter in a PCI slot make sure that the extra PCI X connector section does not hit anything on the motherboard Make sure that the 4 wire internal power conn...

Page 14: ...case of the Dynamic Engineering adapter wires can be inserted into the connector holes to connect the corresponding pins of the SCSI connector shown in Figure 2 6 For the Integrative Innovation adapter a connector with these loopback connections should be made to be attached to the alternate SCSI connector on this adapter shown in Figure 2 7 Figure 2 6 Dynamic Engineering adapter loopback wires in...

Page 15: ...module revision number is printed on the silkscreen along the left edge with the bezel plate towards you of both sides of the module as shown in Figure 2 8 The logic revision number is affixed to the Xilinx boot PROM U39 as shown in Figure 2 9 Figure 2 8 SigC641x module revision number Figure 2 9 SigC641x logic revision number ...

Page 16: ...een which is located next to the module status LEDs marked D1 D16 on the module silkscreen and is shown in Figure 2 10 below The clock rate can also be determined from the part markings on the C6415T processors e g 7E3 for 720 MHz and 1GHZ for 1 GHz The SDRAM clock rate is the processor clock rate divided by 6 which would be 120 MHz for 720 MHz processors and 166 67 MHz for 1 GHz processors Figure...

Page 17: ...nd configuration procedures and requirements documented here may also apply to other server enclosures 3 1 HP DL380p Proliant Series Figures 3 1a and 3 1b below show a SigC6678 64 card installed in an HP DL380p Gen8 server Note the power cable required to connect the card to the 12V connector on the riser Figure 3 1a SigC6678 64 card installed in DL380p server side angle view Figure 3 1b SigC6678 ...

Page 18: ...wn in Figure 3 5 below in the picture the HP cable is on the left with a bar code tag 3 2 Supermicro 1U Figure 3 2 below shows a four 4 SigC6678 32 cards installed in a Supermicro 1U server In this case an unusual narrow motherboard and dual slot riser configuration makes it possible to insert PCIe cards on both sides of the server Note that for SigC6678 32 cards no additional power cables are use...

Page 19: ...64 cards to be installed Figure 3 3 SigC6678 64 card installed in a 1U server top view with 6 pin external power connection highlighted red square Note that it s also possible to mix and match cards for example one SigC6678 32 card and one SigC6678 64 card installed on the same riser or otherwise installed in different PCIe slots in the same server ...

Page 20: ...al power connection 3 4 External Power Cables Figures 3 4 and 3 5 below show different external power cables that can be used with SigC6678 64 cards for example in tower or other traditional PC box enclosures Note that for SigC6678 32 cards no additional power cables are used Figure 3 4 External power cable for SigC6678 64 cards that connects to standard 4 pin peripheral power cables inside a desk...

Page 21: ...igure 3 5 below shows external power cables that mate with a server internal riser card Note that typically yellow wires are 12V and black wires are Gnd Figure 3 5 External power cable for SigC6678 64 cards that connects to an internal riser card If for any reason you are unsure about which connector to use and you want to absolutely verify voltages prior to card installation a simple test step is...

Page 22: ...ows voltage pin assignment for the 6 pin end of cables shown in above figures and pictures Notes about Figure 3 6 View is facing the connector i e as if you re standing on the card looking at the end of the cable COM means Common or Gnd Some cables may break out the 6 wires for example Figure 3 4 above shows the 6 wires distributed among 3 peripheral power connectors in 2 wire pairs one 12V wire a...

Page 23: ...s there is not always a clear physical boundary for instance in an SoC device with one or more ARM cores and one more compute intensive cores the ARM cores would be the Linux host and the compute cores the target The table below shows host and target software folders after installing the distribution rar files Subfolder Name Type Description Comments DirectCore Host Key subfolders include driver l...

Page 24: ...net DSP etc RTAF Real Time Algorithm Framework provides target software support for host software including DirectCore software CIM software and user defined projects The target software rar file consists of source code and other necessary files to build with Texas Instruments command line code generation build tools For more information about RTAF see section 4 5 below RTAF Software Usage Configu...

Page 25: ...re for multicore CPU or other target hardware e g CIM accelerator DSP card video or telecom card network processing card neural net card etc Note that the various supported multicore CPU and other target hardware types are collectively referred to throughout the User Guide as targets and code that runs on the target as executable target code and files or run time code For older generation SigC641x...

Page 26: ...rarchy for SigC641x modules For SigC641x cards TI code generation and configuration is not automated and must be performed with TI s Code Composer Studio IDE environment using project files included in the target software In this case the target rar file has to be installed on a Win machine as shown in Figure 4 2b above ...

Page 27: ...ctCore driver instead these calls are made by DirectCore libraries via user application API calls Applications that make user space calls directly to the driver are not supported Note 1 To build the DirectCore driver certain Linux kernel header files are required These are available if the kernel devel RPM has been installed and a symlink has been created for usr src linux See section 4 1 1 below ...

Page 28: ...build load and verify process In Figure 4 3 areas outlined in red show a SigC6678 32 card installed 4 6678 devices 32 CIM cores total and a SigC641x module installed on a PCIe adapter card 8 C641x devices 8 CIM cores total In this case both cards were installed in the same server simultaneously Note If the ls dev command does not show device entries as noted above you may need to reboot the system...

Page 29: ... symlink for usr src linux must be created Instructions for these steps are given below Note that full kernel source code is not required as the DirectCore driver is an external driver not incorporated within the kernel that can be loaded and removed as needed after the kernel is already booted and running i e loadable kernel module or LKM Note The commands below assume that you are logged in as r...

Page 30: ...stall linux headers x86_64 for 64 bit Ubuntu 2 Step 2 In addition to installing the kernel devel package a symlink for usr src linux must be created using a command similar to the following root host ln s usr src linux xx xx xx usr src linux where xx xx xx matches the kernel version returned by the uname r command shown above After the symlink is created the following ls list command can be used t...

Page 31: ...building either an archive a or shared object so file should be copied to the default system library directory typically usr lib Note that the Makefiles do this automatically but it s always a good idea to verify that library files are being copied otherwise application layer programs that use DirectCore APIs may not build correctly For each library use the following build sequence cd lib libname ...

Page 32: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 32 109 Figure 4 5 DirectCore library rebuild process After building each library resulting library filenames should be ...

Page 33: ...benmgr a or libenmgr so libhwmgr a or libhwmgr so libhwlib a or libhwlib so libcimlib a or libcimlib so libfilelib a or libfilelib so libtdmlib a or libtdmlib so libsessionmgr a or libsessionmgr so libvoplib a or libvoplib so Note See notes above about whether to build these libraries ...

Page 34: ... connection is required Can be used to validate the card driver and library installation fftTest None Example of algorithm parallelization and acceleration videoTest None Example of video codec acceleration this example does video encoding streamTest Ethernet Example of high performance video transcoding and streaming UDP RTP streaming output can be routed to a mobile device for example an Android...

Page 35: ...gC641x_C667x memTest make To run memTest first enter memTest h This will bring up the help menu showing command line options that can be used to configure the test program and SigC641x or SigC667x hardware memTest command line options are shown below indicates mandatory entry c string card designator e g cSIGC66XX or cSIGC64XX B num block size d diagnostic test default if d r or z not entered D di...

Page 36: ...low is a screen capture of a successful memTest run for 3 cores by running the following command memTest m7 d cSIGC66XX or memTest m7 d cSIGC64XX The screen capture in Figure 4 6 below shows an incrementing loop counter at the top of the terminal display and the error counters for the first 3 cores remain zero as the loop counter value increases The remaining error counters represent cores not inc...

Page 37: ...4 37 109 Figure 4 6 memTest running diagnostic test for 3 cores on SigC667x or SigC641x hardware Figure 4 7 below is a screen capture of a memTest diagnostic run for 32 cores using SigC667x hardware by executing the following command memTest cSIGC66XX d m0xffffffff B98304 P ...

Page 38: ... 2014 38 109 Figure 4 7 memTest running diagnostic test for 32 cores on a SigC667x card Figure 4 8 below is a screen capture of a successful random block memTest run for 3 cores using SigC641x hardware by executing the following command memTest m0xa8 r B204 n20 cSIGC64XX ...

Page 39: ... above command the n20 parameter specifies the test to run for 20 iterations Without the n parameter the test runs for one iteration by default Figure 4 9 below is a screen capture of a successful random block write only test of onchip core memory i e core specific L2 memory for 32 cores by executing the following command memTest cSIGC66XX B98304 pt P r m0xffffffff Moc n10 W ...

Page 40: ...that performance measurement has been specified using the p option in this case specifically the pt option which measures transfer time only excluding any intermediate software functions such as data preparation error checking etc Figure 4 10 below is a screen capture of a successful random block test of onchip shared memory i e MCSM or multicore shared memory for 32 cores using SigC667x hardware ...

Page 41: ...increase measured performance however improvement is marginal beyond some point Smaller block sizes are likely to decrease performance Using SigC667x as an example from 1 MByte down to 100 KByte block size performance may decrease about 40 MByte sec at 50 KByte block size performance may decrease another 35 MByte sec and at 10 KByte block size performance may decrease as much as 200 MByte sec and ...

Page 42: ...of code necessary to gain basic target card module connectivity and data transfer Note The C class is only supported for SigC641x To build the boardTest program enter the following cd DirectCore apps SigC641x_C677x boardTest make default uses C source code or enter the following make cpp uses C source code Currently the make is the standard default option and should be tested first Before running ...

Page 43: ...ion Figure 4 11 below is a screen capture of output from the boardTest test program executed using the following command for a SigC667x PCIe card boardTest m1 f1250 ebdtest out cSIGC66XX for the following command for a SigC641x PCIe card or PTMC module boardTest m1 f1000 ebdtest out cSIGC64XX The screen capture in Figure 4 11 shows a sequence of low frequency sinusoidal signal values The values ar...

Page 44: ...ress the q Quit or ESC keys Note you can also exit using Ctrl C but using the interactive keyboard commands is preferred as that allows the test program to free de allocate the card handle close its instance of the driver and perform other clean up operations This helps to maintain clean host Linux server operation and avoid memory leaks driver errors etc ...

Page 45: ...h sign are mandatory f num Device clock rate in MHz e g f1000 m num Core select bit mask e g m1 means core0 m2 means core1 Note in this test only one bitmask values of 2n 1 can be selected specifying the number of cores to run in parallel e string Target executable file in ELF or COFF format e g efft out c string Card designator e g cSIGC66XX a num Algorithm flag 0 parallel FFT 1 serial FFT defaul...

Page 46: ...lelized method based on Bailey s Four Step algorithm 1 which factors an FFT of order No into an NxM matrix of FFTs where N and M are as close as possible to No FFTs in the matrix are then run on multiple target CPU cores concurrently A small FFT order is used for the test to allow results to conveniently viewed and the test to be repeated in serial non parallelized FFT mode in order to compare val...

Page 47: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 47 109 Figure 4 12 Example fftTest display output ...

Page 48: ... options with sign are mandatory f num Device clock rate in MHz e g f1000 m num Core select bit mask e g m1 means core0 m2 means core1 Note in this test only one core can be selected at a time e string Target executable file in ELF or COFF format e g evideo out c string Card designator e g cSIGC66XX i string input waveform file in yuv format s num Scaling option v Run in verbose mode h Display thi...

Page 49: ...line Num frames encoded in Figure 4 13 above If videoTest hangs for any reason you can exit by pressing the q Quit or ESC keys Note you can also exit using Ctrl C to exit test programs but using the interactive keyboard commands is preferred as that allows the test program to free de allocate the card handle close its instance of the driver and perform other clean up operations This helps to maint...

Page 50: ...ight Signalogic 2012 2014 50 109 Figure 4 14 Example of encoded videoTest output In the above screen capture H 264 encoded data has been stored to a file and then played back for test comparison purposes using the Videolan VLC open source video player ...

Page 51: ...ld the appTest program enter the following cd root Signalogic_2012v4 DirectCore apps SigC641x_C667x apps appTest make Note that the libraries mentioned in section 4 2 above including Session Manager must be built before appTest can be built successfully To run the appTest program first enter appTest h This will bring up a help menu Command line option syntax options with sign are mandatory c strin...

Page 52: ...grams section for a table showing the corresponding CCS projects and target executable code files for each host test program 4 3 5 1 appTest Output Description Figure 4 15 below is a screen capture of a successful appTest run executed using the following command appTest m1 f720 etmsc64xx out cSIGC64XX t C The screen capture in Figure 4 15 below shows continuous target multicore CPU memory diagnost...

Page 53: ... keyboard commands include Main Level A Algorithm Mode Control C Show list of currently active call IDs D Display diagnostic data currently shows per channel state and flag information target code probe points and IP UDP RTP packet information F Freeze unfreeze continuous target data display L Load media M Show list of currently active media IDs ...

Page 54: ...ent modes including half duplex full duplex wav file data or microphone source and with flexible RTP parameters such as 16 bit linear and 8 bit compressed payload formats and variable payload lengths Following are some command line examples 1 Here the command line specifies source data as microphone and destination as a UDP RTP stream to IP address 10 0 0 53 using 8 bit uLaw RTP payloads smic d10 ...

Page 55: ...t program open a console application window e g run Cmd under WinXP go to the directory on which you installed the executable and run rtpaudio followed by command line entries such as those shown above Note For detailed information about the RTP Audio Test Program please refer to the RTP Audio Test Program Users Guide which contains system diagrams program usage screen captures RTP payload and hea...

Page 56: ...IU Line loopback HW400c2 RTX CHASSIS T3 8 192 MHz clock 8 kHz frame clock RX TX DSP loopback GbE Backplane TX RX From T3 Demux output see page1 2 1 3 Figure 4 16 TDM call equipment and setup T8110 Framer WTRB500 RTX CHASSIS Signalogic Inc Rev 5 Title Push To Talk Test Setup Project WTRB Compatibility Copyrights Signalogic 2008 DSP Farm Note The HW400c2 and WTRB500 are installed in the same RTX cha...

Page 57: ...t3 type the following cd usr src linux make modules make modules_install To load the DS3 driver type modprobe wan256t3 To unload the driver type rmmod wan256t3 To see driver options type modinfo wan256t3 2 Run the DS3cfg script using the following command line sequence cd BaseFolder DS3 DS3cfg The DS3cfg script performs basic configuration and initialization of the TECT3 framer and T8110 devices o...

Page 58: ...odified A version of the script called DS3cfg_mapping is available as an example of how to do this look near the end of the script 3 Note this step is optional Updated test procedures do not require this step Initialize a call using the CPU blade software WTRB500 media board and Inet signaling test generation unit connected to SS7 signaling module located on the CPU blade At least one call has to ...

Page 59: ...on all channels logic loopback disabled TDM mapping set to non reversed which assumes the Motorola WTRB500 board is not present in the T3 circuit No calls connected No medias downloaded into target multicore CPU memory 4 3 5 4 Interactive Command Summary Below is a summary of interactive key commands available when running the test program Commands are in two levels a Main level and a Second level...

Page 60: ... entry of IP address for IP call testing ____ L Enable logic loopback of CTBus streams default disabled ____ N Enable CTBus stream registers default enabled ____ P Toggle debug prompt enable ____ Toggle IP Test Mode default enabled ____ W Toggle whether WTRB500 board is in series in the T3 circuit default is not in the circuit ____ V Toggle verbose mode for diagnostic data display default is disab...

Page 61: ...c loopback but not with target voice processing Press the d key to re enable target voice processing 3 If in Operating Mode then exit by pressing the o key again Use the s key to set up calls The call setup prompt entry is of the format brackets indicate optional entry type Id a b dsp where type is Call Type either c for conference or p for PTT Id is an optional Call Id a and b specify call leg in...

Page 62: ...umed Normally this is zero first target CPU Note that partial entry is allowed for call and call leg input For example when creating calls if no endpoint information is given then the first available endpoint is assigned If no channel is specified then the first available channel is assigned If no call leg source information is given then the first available T1 is assumed Call legs may be added to...

Page 63: ...igned given explicitly In the sixth call each leg is set up separately Notes about the above call setups Call Ids 1 thru 4 are assigned for first 4 calls a Call Id value of 5 is given explicitly for the fifth call but only one leg of the call is active so this call ID is reserved A Call Id value of 10 is given explicitly for the sixth call only one call can be set up each time s is pressed Call Id...

Page 64: ...n indicates that PTT talker voice was detected and PTT buffering started upon voice detection The Delay version indicates that PTT buffering started after some non voice when no PTT talker voice was detected currently this includes a dead channel which is useful for lab testing and a user specified arbitrary delay Upon creation of the PTT call a PTT buffering start VAD event should be displayed Ab...

Page 65: ...rs can be assigned to a PTT call 6 Now press c key to verify the active call list The test program should display currently active calls as shown in Figure 4 20 below Figure 4 20 Active call list display Note that Call Id s are assigned in the order of call setup unless Call Id is specified explicitly during the call setup entry When a call is deleted using the tear down command then the deleted C...

Page 66: ...hat the channel endpoint entry specification exactly matches the talker leg of the existing call 8 Using test system equipment as shown in Figure 4 16 above or similar equipment verify one or more currently active TDM calls using handset phones 9 To set up IP calls take the following steps First enter source and remote IP addresses and UDP ports as shown below 1 press o to see operating control mo...

Page 67: ...ide Rev B7 Copyright Signalogic 2012 2014 67 109 Figure 4 21 Setting up an IP call 10 Next press s to set up an IP call using the following command line c i9 13 After setting up the call press Enter you should see the following screen ...

Page 68: ...etting up a TDM to IP call 11 Set up three 3 more IP calls as shown below c 16 i17 c 18 i19 c i22 23 12 Now press c key to verify the current call list The test program should display all currently active calls as shown in Figure 4 23 below Note that IP channels are indicated with ip in the src column ...

Page 69: ...e of call and headsets connected to the WinXP PC sound card for IP side of call For example run this RTP Audio command line RtpAudio s10 0 1 62 16384 dsnd u8 f RtpAudio smic d10 0 1 62 16384 u8 f Notes 1 Above IP addresses and UDP ports are only examples These values may be different from one test system to another 2 Make sure the WinXP machine IP address matches one of the remote IP addresses pre...

Page 70: ...an one WinXP machine For detailed information about the RTP Audio test program please see the document RTP Audio Test Program Users Guide Figure 4 24 Full duplex IP call testing using RTP Audio test program 14 Verify effects of AGC by pressing the a key Algorithm Mode and then the g key several times and noting slight difference in voice levels and background noise When you do this you should see ...

Page 71: ...en the output trace green will show a flat line zero pattern for any unused channels If AGC is active then the output trace will show a constant non zero pattern for any unused channels Remember that if N calls are set up then unused channels start after 2 N channels on the scope display 15 Exit Algorithm Mode press a key again and then press the d key to display a diagnostic readout showing curre...

Page 72: ...sections of target code IP call transmit send packet values RTP payload only and a target channel table which shows a 32 bit encoded channel information value for each channel channels 0 to 127 Channel information values have the following format 31 28 27 24 23 16 15 8 7 4 3 0 VAD Score DTMF Detect Call Index Channel Flags Call State Channel Source Encoded field values are explained in the table b...

Page 73: ... 1 12 13 0 14 15 D 1 Call Index Index of call to which this channel is connected A call can have multiple nodes so an index value of N indicates this channel is a node of call N 1 255 Channel Flags Indicators for activity on the channel Note that flags use power of 2 encoding as more than one channel flag can be active at any one time 1 Indicates channel is a PTT listener 2 Indicates channel is a ...

Page 74: ...e of 28 T1 streams on the DS3 T3 module 3 In basic IP mode IP channels are processed by the host CPU i e the appTest program reads writes IP UDP RTP packets from target CPU memory and sends receives the packets over the network In Advanced IP mode IP channels are processed by target CPU code i e target CPU code sends receives IP UDP RTP packets using the GbE interface on the SigC641x module In bot...

Page 75: ...ys on a connected handset and verify that you see DTMF event display as shown in Figure 4 27 below Figure 4 27 DTMF event display Note that DTMF events are detected only on channels currently allocated for calls i e if a channel is not connected to a phone then no DTMF events are detected or displayed ...

Page 76: ...he following waveform file formats are supported wav PCM 16 bit linear wav u Law 8 bit wav A Law 8 bit tim PCM 16 bit linear ton PCM 16 bit linear after de compression Note that only mono single channel waveform files are supported 18 Press m key to show a list of loaded medias as shown in Figure 4 28 below Figure 4 28 Example list of loaded Medias 19 Press p key to play medias The media playout p...

Page 77: ...oad delete a media press the u key and enter the Media Id to be deleted Media Playout Notes A media playout completed event is displayed when each media playout is complete An example is given in Figure 4 29 below If a media playout is attempted on a channel already playing a media then an error message is displayed If a media is played on a channel not used in a currently active call then a tempo...

Page 78: ...s to verify calls continue to function correctly 22 Measuring CPU usage open another terminal window use putty again and connect to the HW400c 2 board After you login and get a command line prompt enter the command top You should see the CPU usage of different processes shown as a percentage Figure 4 30 below shows CPU usage by the appTest process as varying from 3 to 4 ...

Page 79: ...running Linux Top process 23 Use t key to tear down calls 1 7 and call 10 Note effects on scope if connected Verify using handsets that no calls are active per Channel loopback state is restored 24 Press c key again to verify no calls are active Figure 4 31 shows the call list after the calls are tear down ...

Page 80: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 80 109 Figure 4 31 Call list after call tear down ...

Page 81: ...nt Verification If a digital scope is connected to the CTBus between the DS3 module and SigC641x modules then the scope should show a display similar to Figure 4 32 below Figure 4 32 Capture of active CTBus data between SigC641x and DS3 modules 26 When necessary press the q key to exit the appTest program ...

Page 82: ...6 for example if you re running Ubuntu 14 xx This issue can arise since the TI installer doesn t appear to work for some 64 bit Linux distributions but it will work with correct 32 bit libs installed 4 4 1 TI Code Generation Tools Download The first step is to download TI Code Generation tools commonly referred to as CG Tools Go to the following page https www a ti com downloads sds_support TICode...

Page 83: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 83 109 Figure 4 33 TI Code Generation Tools download page ...

Page 84: ...The version of XDCtools installed should be 3 22 04 46 or higher These version numbers have been tested in Signalogic labs although older versions may still work 2 IPC Interprocessor Communication is currently not used by DirectCore and CIM software but may be in the future For C667x devices IPC includes SRIO and HyperLink The SigC6678 cards have SRIO connections between all C667x devices SRIO is ...

Page 85: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 85 109 Figure 4 34 TI software folder hierarchy including Code Gen tools SYSBIOS IPC XDCtools and PDK ...

Page 86: ... can be downloaded separately for example to upgrade one of the components without downloading all of BIOS MCSDK To download components separately go to the following page http software dl ti com dsps dsps_public_sw sdo_sb targetcontent bios sysbios index html Note that currently PDK can t be downloaded separately and must be obtained via BIOS MCSDK download ...

Page 87: ...rithm functions CIM software support 4 5 1 RTAF Configuration Options The RTAF software build process supports the following pre processor definitions Pre Processor Definition Description _USE_CM_ Enables Call Manager support _PERIPH_TEST_ Enables POST and other test options for peripherals _BIOS_ Enables SYSBIOS compatibility in the build process _CIMF Enables support required for CIM software bu...

Page 88: ...41x supports audio analog I O TDM H 110 and user defined interfaces Not currently supported on SigC667x Telecom Serial Port or TSIP may be supported at a future point GPIO Supports both SigC641x and SigC667x Flash devices Typically connected to EMIFB interface FPGA Logic If present on the card for example host CTBus FPGA on SigC641x modules UART If present on the hardware RS 422 If present on the ...

Page 89: ...oftware is included under the C6xxx subfolder There are a few fundamental points about RTAF development and host platform to keep in mind 1 RTAF software supports SigC641x modules installed in Linux systems but SigC641x RTAF software is not generated or rebuilt on a Linux system Instead the software must be maintained on a WinXP or Win7 8 system with Texas Instruments CCS software installed Conver...

Page 90: ...alogic_2012v4 mCPU_target C6xxx BIOS cStandard 2 Then use the make command which invokes the contents of the Makefile file Note that this file will be overwritten if when a host side CIM build script is used Building with CIM To build with CIM host side software use the CIM script cimpp sh located in root Signalogic_2012v4 CIM cimrt The command cimpp sh h will display the command line options An e...

Page 91: ...ment The first one can be edited to change the platform used by changing the p parameter The second one builds the source files in the cimf_build lst file If CIM software is used by host applications then 2 additional source files will be added to the command to be built The last tool is the linker which uses ORDERED_OBJS and all the obj files in the directory root Signalogic_2012v4 mCPU_target C6...

Page 92: ...y the system PATH environment variable as follows export PATH PATH root Signalogic_2012v4 CIM cimrt this can be done each time the system boots or made an automatic boot setting inside the shell profile configuration file for example etc profile etc 2 cd change directory to the folder with your input C source files 3 Give a command in the following form to run the CIM pre processor cimpp file1 c f...

Page 93: ...then default CardType containing CPU matching AccelType is used Y SIGC6678 Signalogic 32 core C6678 accelerator Y SIGC6678 64 Signalogic 64 core C6678 accelerator Y Note that it s also possible to run the CIM pre processor from an arbitrary location for example cimpp s root Signalogic_2012v4 CIM apps test_demo ffmpeg_demo px86 ati66x cSIGC66XX file1 c file2 c 4 6 2 h264_encode demo To run the CIM ...

Page 94: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 94 109 Figure 4 37a h264_encode CIM build process output display ...

Page 95: ...1 27 15 SigC667x SigC641x User Guide Rev B7 Copyright Signalogic 2012 2014 95 109 Figure 4 37b h264_encode CIM build process output display cont ...

Page 96: ... 109 Figure 4 37c h264_encode CIM build process output display cont After the CIM build process completes the h264_encode executable file will be created and can be run as a typical Linux program h264_encode which should produce screen display output similar to Figure 4 38 below ...

Page 97: ...ount 740 11 DSXRunCard Successful Core 1 Finished Core 2 Finished Core 3 Finished Core 4 Finished Core 5 Finished Core 6 Finished Core 7 Finished Core 0 Finished Reading output video data saving to file C66x testrun 0 0x85f95c 9003 C66x cores error code 0x85ec28 0 numFramesEncoded 0x8597b4 40 h264_encode Figure 4 38 h264_encode demo output display Note that on the h264_encode folder only the files...

Page 98: ...each time the specified ISR GPIO TX or RX is entered are displayed on each display updated 2 FPGA revision numbers and memory symbol addresses are displayed once Sync data for MCBSP and MCBSP_GPIO test modes is displayed once A message indicating a signal was received with the DSP number that HINT was generated on is displayed each time the signal handler runs f N Sets the processor clock rate in ...

Page 99: ...trl register in FPGA 2 Takes a 32 bit value e g r0x300 the default value with the following bit definitions 31 11 Reserved 10 Group B Strobe Trigger Routing 0 rev 2 4a 1 rev 2 4b 9 PN4_FSX1_B direction 0 output to PN4 1 input from PN4 8 PN4_CLKX1_B direction 0 output to PN4 1 input from PN4 2 Group A Strobe Trigger Routing 0 rev 2 4a 1 rev 2 4b 1 PN4_FSX1_A direction 0 output to PN4 1 input from P...

Page 100: ...isplay DSP FPGA and on chip memory tests are then run and DSPs are reset Next the SDRAM on each selected DSP is checked and results are displayed Figure 5 1 below shows an example command line input followed by the first set of display and the SDRAM test results for DSP 0 This was run with the command pn4Test m0x11 f1000 etmsc64xx_rtaf_ccs3 out cSIGC64XX r0x300 MGPIO d2 Figure 5 1 pn4Test initial ...

Page 101: ...e driver to be reloaded The serial port data counts up by 1 and wraps at 0xff for MCBSP test mode and wraps at 0xffff for UART test mode This data is stored in a circular buffer with 64 elements DSP code fills the buffer asynchronously from host reads so the current write position may be apparent by a jump in the numbers When this occurs the difference between these numbers should be 63 GPIO data ...

Page 102: ...rors may be seen on the data words during the first 40 ms of operation depending on when the first and subsequent data words are sent Errors will not occur after the first 40 ms This initialization delay compensates for differences in initialization code resulting in group A and B DSPs coming out of BIOS initialization at different times Figure 5 3 pn4Test MUART_GPIO d2 data display Figure 5 4 sho...

Page 103: ...12 2014 103 109 Figure 5 5 shows the data display for MCBSP_GPIO test mode with the details disabled Figure 5 5 pn4Test MMCBSP_GPIO d0 data display Figure 5 6 shows the data display for GPIO test mode with details level set to 1 Figure 5 6 pn4Test MGPIO d1 data display ...

Page 104: ...on r as outlined in section 3 During the DSP initialization the test mode based on the entered command line parameter is set on the enabled DSPs This determines which devices of the DSPs are initialized and at what rate Table 5 1 below summarizes the rates used based on the test mode Test Mode Group A DSP TX Rate Group B DSP RX Rate Serial Word Size GPIO Sampling Rate MCBSP 1 MHz 1 MHz 8 bit N A U...

Page 105: ...iming Diagram Not to scale 5us 100ns 1us 3 156 4us 200ns Strobe 2 Strobe 1 Strobe Trigger 3 10 Hz DSP Group A DSP Group B CLKX1_B FSX1_B GPIO In Mode Serial Out Mode External Loopback for Testing NC NC FSX1_A CLKX1_A JP2 58 59 26 25 56 55 53 20 19 62 64 31 29 61 28 65 32 67 14 23 49 50 17 16 52 DSP FPGA Connections Strobe Timing Logic SigC641x based Preliminary DSP Support Design rev 2 4a Page 2 o...

Page 106: ...sign rev 2 4b Page 2 of 2 Jed Kelsey 27 Jan 2012 rev 2 3 quoted version 31 May 2012 rev 2 4a revised SigC641x signal names 15 Jun 2012 rev 2 4b FSR Trigger connection to PN4 pins Loopback Tests TEST_ENABLE_A DR1 in GPIO mode is used to verify PN4_PWR_ENABLE_A operation via loopback DSP4 DR1 input serial receive mode verifies that PN4_SERIAL_CMD_A is transmitted correctly DSP4 CLKX1 FSX1 inputs GPI...

Page 107: ...place after McBSP1 is initialized on both DSPs The group A DSP sends a sync character that cannot be duplicated through a shift of less than 8 bits we use 0x3c as this character for 1 ms When the group B DSP receives a data word it checks if the word matches the sync character If the sync character was not received McBSP1 is placed in reset for about an eighth of a bit period then re enabled to ch...

Page 108: ...e delays caused by CPU stalls 900 KHz is the highest rate at which all test modes reliably and consistently operate An issue where BIOS crashes arises when the BIOS enables multiple interrupts concurrently causing multiple ISRs to be called at around the same time As a workaround to this issue initially the timer operates at a frequency of 16 Hz then reinitializes to the 900 KHz sampling rate afte...

Page 109: ... via memory locations by the DSP In the cases of uNotifyMode 1 and 2 the signal handler runs whenever a HINT notification signal is received and calls the corresponding callback function which clears the HINT and adds the DSP number that the HINT arrived on to the DSP queue DSP numbers in the DSP queue signify a pending DSP buffer data collection event In the cases of uNotifymode 0 and 1 the corre...

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