Examples and register assignments
4.3 Registers
SIMATIC PCIe DIO4
24
Compact Operating Instructions, 11/2011, A5E03493449-01
INPIF: Input interrupt flag register (BASE + 0x0110)
Bit
Access Name
Default Description
31..0
RWC
IFx
0
Each bit reflects the interrupt state of the corresponding
input. If a bit is set, STATUS.IIF is set. If the bit is written
with "1", the bit is reset as well as the corresponding
IFRE/IFFE bits.
INPIFR: Input interrupt flag register, rising edge (BASE + 0x0120)
Bit
Access Name
Default Description
31..0
RWC
IFREx
0
Each bit reflects the interrupt state of the rising edge of
the corresponding input. If a bit is set, STATUS.IIF is set.
If the bit is set, the corresponding INPUTIF.IF is set. If
the bit is written with "1", the bit is reset.
INPIFF: Input interrupt flag register, falling edge (BASE + 0x0130)
Bit
Access Name
Default Description
31..0
RWC
IFFEx
0
Each bit reflects the interrupt state of the falling edge of
the corresponding input. If the bit is set, the
corresponding INPUTIF.IF is set. If the bit is written with
"1", the bit is reset.
INPxC: Input x configuration register (BASE + (x*8))
Bit
Access Name
Default Description
63..16 RO
0
Reserved
15..10 RW
FSRATE 0
Sample frequency input filter f
s
= 62.5 MHz / (FSRATE
<< 12).
9..8
RW
FTHRES 0
Sample threshold input filter. 00: 1 sample, 01: 3
samples, 10: 5 samples, 11: 7 samples.
7..4
RO
0
Reserved
3
RW
ENFEI
0
Enables an interrupt with a falling edge of the input
signal. If the bit is set and a falling edge is detected at
the input, the corresponding bit is set in INPIFF.IFFE.
2
RW
ENREI
0
Enables an interrupt with a rising edge of the input
signal. If the bit is set and a rising edge is detected at the
input, the corresponding bit is set in INPIFR.IFRE.
1
RW
ENF
0
Enables the input filter. If "1", the input is filtered with the
settings of FSRATE and FTHRES.
0
RW
INV
0
If "1", the input signal is inverted before it is processed
further.
