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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
"
The Choice: Enabled or Disabled.
PCI #2 Access #1 Retry
When this item disabled, PCI#2 will not be disconnected until access
finishes (default); On the contrary, PCI#2 will be disconnected if max
etries are attempted without success.
"
The Choice: Enabled or Disabled.
AGP Master 1 WS Write
When this item enabled, writing to the AGP(Accelerated Graphics Port)
is executed with one wait state.
"
The Choice: Enabled or Disabled.
AGP Master 1 WS Read
When this item enabled, reading from the AGP (Accelerated Graphics
Port) is executed with one wait state.
"
The Choice: Enabled or Disabled.
