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SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
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The Choice: 3 or 2.
Bank Interleave
The interleave number of internal banks, can be set to 2 way, 4 way
interleave or disabled. For VCM and 16Mb type dram chips, the bank
interleave is fixed at 2 way interleave.
When the dram timing is selected by SPD, it will be set by the value on
SPD of the RAM module(DDR or SDR).
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The Choice: Disabled, 2 Bank, or 4 Bank.
DRAM Drive Strength
This item enables the system to automatically select its output buffer
drive strength or make it manually selectable by an end user.
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The Choice: Auto or Manual.
DRAM Drive Value
This item enables an end user to manually select the DRAM output
buffer drive strength.
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Key in a HEX number: Min=0000, Max=00FF.
Memory Hole
In order to improve performance, some space in memory can be
reserved for ISA cards.
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The Choice: Disabled or 15M-16M.
P2C/C2P Concurrency
This item allows you to enable/disable the PCI to CPU and CPU to PCI
concurrently.
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The Choice: Enabled or Disabled.
Fast R-W Turn Around
This item controls the DRAM Timing. It allows you to enable/disable
the fast read/write turn-around.
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The Choice: Enabled or Disabled.
