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IRQ 3/4/5/7/9/10/11/12/14/15, assigned to
These items allow you to determine the IRQ assigned to the ISA bus
and is not available for PCI slot.
The choice: Legacy ISA, PCI/ISA PnP.
DMA 0/1/3/5/6/7 assigned to
These items allow you to determine the DMA assigned to the ISA bus
and is not available for PCI slot.
The choice: Legacy ISA, PCI/ISA PnP.
CPU to PCI Write Buffer
When enabled, up to four Dwords of data can be written to the PCI
bus without interrupting the CPU. When disabled, a write buffer is
not used and the CPU read cycle will not be completed until the PCI
bus signals that it is ready to receive the data.
The choice: Enabled, Disabled.
PCI Dynamic Bursting
When Enabled, data transfers on the PCI bus, where possible, make
use of the high performance PCI burst protocol, in which greater
amounts of data are transferred at a single command.
The choice: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are command with zero wait
states.
The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you enable/disable the PCI #2 Access #1 Retry.
The choice: Enabled, Disabled.