Sharp GX15, Service Manual

Page: 105 / 122

GX15
6 – 17
CONFIDENTIAL
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
36 OD1 Input/Output CPU I/F data bus, bit 1
37 HVDD2 – External digital power supply 2 (+1.8/3.0 V)
38 D0 Input Image I/F input data, bit 0
39 GND – Earth
40 DX Input Test terminal (use Low input)
41 CINT Output CPU/ I/F interrupt output
42 GND – Earth
43 SDA Input/Output Artificial I C I/F data line
44 CVDD – Internal core power supply (+1.8 V)
45 D1 Input Image I/F input data, bit 1
46 D2 Input Image I/F input data, bit 2
47 RSTB Input Reset input
48* CBREQ Output CPU I/F DMA request output (Not used)
49 D3 Input Image I/F input data, bit 3
50 D4 Input Image I/F input data, bit 4
51 TEST2 Input Test terminal 2
52 STANDBY Output Stand-by signal output to camera module
53 TEST1 Input Test terminal 1
54 GND – Earth
55 PCLK Input Input pixel clock from camera module
56 HSYNC Input Horizontal synchronous signal
57 D7 Input Image I/F input data, bit 7
58 D5 Input Image I/F input data, bit 5
59* – – Continuity test terminal (Not used)
60 TEST3 Input Test terminal 3
61 ACLOutput Reset signal output to camera module
62 SDC Input/Output Artificial I C I/F clock line
63 HVDD1 – External digital power supply 1 (+3.0 V)
64 GND – Earth
65 VSYNC Input Vertical synchronous signal
66 HVDD1 – External digital power supply 1 (+3.0 V)
67 D6 Input Image I/F input data, bit 6
68* – – Continuity test terminal (Not used)
Pin No. Terminal name Input/Output Description of terminal
2
2
EXCKI
CLKO
SDA,SDC
H,VSYNC
ACL
STANDBY
DSP I/F
DSP control circuit
320x16x2
192x16x1
U Y V Y
Clock control circuit
Bus
I/F
Data
arbitr
ator
Inter
nal
register
Line buffer
for saving
Shared
memory
640x16x8
Line buffer
for display
Format conversion
(e.g. image trimming)
Reduction
Artificial I
2
C
generation circuit
YUV serial/parallel
conversion
(UYVY-YUV)
(UYVY-RGB)
Image processing block
Host I/F
Bus
connection
Host side Camera module side
Image data Control data Other signals