Sharp ER-A460, Service Manual

Page: 25 / 75

Each BAR is composed of 4 byte address. Bit composition is as
follows:
Fig. 6-4
4
is the enable register. The entry registers of the break address are
assigned to
1
,
2
, and
3
. Each bit of address corresponds to each
bit position, writing to
1
,
2
, and
3
is performed without shifting. The
corresponding area is 1MB space of ROS1 and ROS2.
3) SSP register access method
Access to SSP break address register is performed through the tem-
porary register as shown below:
Fig. 6-5
Enable flags can be accessed individually.
Though enable register
4
can be accessed individually, writing to
brake address registers
1
and
2
is performed at the same time as
writing to brake address register
3
through the temporary register.
Therefore, set
1
and
2
to temporary, then write into
3
at last.
Since the temporary register is commonly used by BAR sets, the-
following register setting is performed after completion ofsetting of
each break address register.
3
SSP control method
Access to the enable register and the brake address register is only
possible when writing to them from the CPU.
Information on which brake register the SSP brake is detected in is
read as binary data by reading address FFFFFFH (*1).
Used in an expanded register.
Normally is a reserve bit. Whenreading, fixed to 0.
If there are 32 break registers, binary expression is made with the
above 5 bits, and 0th is “00000
B
” and 31st is “11111
B
.”
When detected simultaneously by two or more break registers,
onewith the smaller BAR number is read as binary data.
The brake signals (NMI) and the above detection data (CMP0~4)
areheld until the above detection data are read. So read should bem-
ade in the NMI sub routine. (Clear by FFFFFFH read.)
*
1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). There-
fore,unnecessary read access in parentheses should not be
performed.
1 2 3 4
A19 A18 A17 A16 A15 A8 A7 A2
EN
Upper bits Intermediate bits Lower bits Enable register
EN (bit7) = 1 Enable
= 0 Inhibit
Don't care for "-----."
< BAR composition >
1 2 3
4
A19 A18 A17 A16 A15 A8 A7 A2
EN
WR
WR
Temporary Temporary
bit 7 6 5 4 3 2 1
0 0 0 CMP4
0
CMP3 CMP2 CMP1 CMP0 (FFFFFFH)
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