Sharp ER-A460, Service Manual

Page: 21 / 75

3. Clock generator
1) CPU (HD64151010FX)
Fig. 3-1
Basic clock is supplied from a 14.7456MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) HD404728A91FS CKDC6 oscillation circuit
(Display-PWB)
Fig. 3-2
Two oscillators are connected to the CKDC6.
The main clock X2 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC6 goes into the standby mode
and the main clock stops.
The sub-clock X1 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC6 as signal RESET to reset
the devices.
This circuit mo24V supply voltage.
The voltage at the (–) pin of the comparator GL393 is always main-
tained to 5.1V by means of the zener diode ZD5, while +24V supply
voltage is divided through the resistors R19, R20, and R21, and is
applied to the (+) pin. When 24V is in supply, 6.8V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +5.1V, which
causes POFF to go low, thus predicting the power-off situation.
The STOP signal from the CPU is converted into the RESETS signal
by the CKDC6.
The RESETS signal from the CKDC6 is converted into the RESET
signal at the gate backed-up by the VRAM power, performing the
system reset.
CPU
(HD64151010FX)
99
98
XTAL
EXTAL
14.7456MHz
X1
43
46
45
15PCH 15PCH
HD404728A91FS
C15 C14
CKDC 6
OSC1
R22
1M
X2
4.19MHz
CL2
CL1
X1
32.768KHz
2
1
3
42
OSC2
+
-
/POFF
5
6
7
4
8
B
IC2
GL393
C16
1000P
D8
1SS133
C15
1µ 50V
+
ZD5
MTZ5.1A
R21
9.1KG
R20
15KG
R23
56K
R22
2.7K
R24
2.7K
R19
8.2KG
+24V +5V
POFF
CPU
72
IRQ0
89
RESET (FROM CKDC 6)
STOP (TO CKDC 6)
MPCA6
13 48
1
IR
Q
0
54
IN
T
0
VRAM
IC3 IC3
C22
RESET
R25 C21
RESETS
STOP
CKDC6
– 20 –