Sharp ER-A460, Service Manual

Page: 29 / 75

1) Power on/off sequence
Fig. 9-2
Hatched area indicates logic unstable.
<At power on>
When +24V power rises, the signal POFF is forced high (A), by which
time the +5V supply becomes stable. The CKDC6 monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA6 have been initialized to high, re-
spectively (C). Thereafter, the CKDC6 sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC6 sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC6 sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.
<At power off>
When +24V power drops, POFF goes low (H).
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When STOP goes low, the CKDC6 sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.
2) Key and switch scanning
Strobes ST0 ~ ST3 are decoded on the keyboard by two 74LS138 3-
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B, and KR3B.
To minimize interfacing lines between the CKDC6 and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDC6 on the return lines of KR0 ~ KR3.
Timing ST
Fig. 9-3
The mode switch in provided with a special return line MODR, apart
from the above return lines.
In the same manner, the clerk, paper feed key (J/R), and receipt
on/off switches use CFSR as the return line.
3) DISPLAY CONTROL
Fig. 9-4
CKDC6 directly drives the 7-segment display unit and the dot display
is driven via M66004FP.
<7-segment display>
Fig. 9-5
A
B
C
D
G
I
J
E
F
H
+5V
POFF
RESET
STOP
SHEN
SCK
+24V
12.45ms
778µ S
10µ S 10µ S 10µ S
KR0A
KR3A
KR0B
KR3B
80µ S
ST3
S15
ST2
ST1
ST0
S14
ST0
KEX0
KEX1
KR0~KR3
S//
RES
DSO
DSCK
DCS
+5V
DG0~
DG11
Display
controller
M66004
FP
DDIG
SO2
SCK2
SDISP
SA~SG
DP,ID
G1~10
7SEG-Display
D0~D35
DOT-Display
16
CKDC 6
976µS
15µS
44.8µS
58µS
Gm
SA,SB,SC,SD
SE,SF,SG
DP,ID
Gm+1
976µS x n
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