MD-MX30/MX30W
– 88 –
Figure 88-1 BLOCK DIAGRAM OF IC
EFM
AGC
DIFF
DIFF
BIAS
LPF
HPF
ADIP
AGC
LOGIC
RF2
RF1
RF4
RF3
REFI
REFO
RFADD
TCGI
AIN
BIN
EIN
FIN
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
RESISTOR & SW
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
ADIPI
ADIPO
NC
ADLPFO
22KO
22KI
WBO
TCGO
AOUT
BOUT
EOUT
FOUT
POUT
GOUT
ATTR
EFMAGI
EFMAGC
AGND
AVCC
EFMI
EFMO
RF2-1
ADAGI
ADAGC
BIAS
AVCC
STBY
DISC
SGAIN
AGND
DGND
DTEMP
LATCH
CLOCK
DATA
DVCC
IC1101 VHiiR3R55//-1:RF Signal Processor (iR3R55)
IC1202 RH-iX2474AFZZ: 4Mbit D-RAM (iX2474AF)
Pin No.
Function
Terminal Name
1, 2
I/O1, I/O2
Data input/Data output
3
WE
Write enable
4
RAS
Row address storobe
5
A9
Address input
6-9
A0-A3
Address input
10
Vcc
Power (3.3V)
11-15
A4-A8
Address input
16
OE
Output enable
17
CAS
Column address storobe
18, 19
I/O3, I/O4
Data input/Data output
20
GND
Ground
Figure 88-2 BLOCK DIAGRAM OF IC
4
RAS
5
17
15
CAS
A0
A9
WE
I/O1~I/O4
20
V
SS
V
BB
17
CAS
Clock Generator
CBR Refresh
Counter
Row Address
Buffer
Memory
Cell
I/O
Selection
Write Clock
Generator
Data Input
Buffer
Data Output
Buffer
Row Address
Buffer
On ChipVBB
Generator
Row Decoder
Column Decoder
Sense Amp.
Word Driver
SELF Refresh
Timer
MN42V4400 ONLY
3
OE
16