SET 89299 Technical Description Download Page 32

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cRIO LVDT 9312 Module

Technical Description

Issue

24/05/2022

Instruction [U8]:

Tx-Data [U8]:

Receive-Data [U16]:

Data Sink:

Read Frequency

(4)

no data

Excit. Frequency. [Hz]

LVDT Controller

This instruction reads the programmed frequency of the excitation voltage. The return data format is a 16bit
engineering value in [Hz].

Instruction [U8]:

Tx-Data [U8]:

Receive-Data [U16]:

Data Sink:

Read Channel A

(6) no data

Ch A Voltage [mV

RMS

]

LVDT Controller

This instruction reads input channel A voltage amplitude. The return data format is a 16bit engineering value with
dimension [mV

RMS

]. This value is NOT for Position calculation and updated only 9 times per Second

Instruction [U8]:

Tx-Data [U8]:

Receive-Data [U16]:

Data Sink:

Read Channel B

(7)

no data

Ch B Voltage [mV

RMS

]

LVDT Controller

This instruction reads input channel B voltage amplitude. The return data format is a 16bit engineering value with
dimension [mV

RMS

]. This value is NOT for Position calculation and updated only 9 times per Second

Instruction [U8]:

Tx-Data [U8]:

Receive-Data [U16]:

Data Sink:

Set Amplitude

(9)

Excit. Amp.[mV

RMS

]

Excit. Amp.[mV

RMS

]

LVDT Controller

This instruction programs the excitation amplitude. The data format is a 16bit engineering value with dimension
[mV

RMS

Valid Amplitude Range: 2000 [mV

RMS

].. 7000 [mV

RMS

]

Summary of Contents for 89299

Page 1: ...er components in the system might not meet the same safety ratings Refer to the documentation of each component in the system to determine the safety and EMC ratings for the entire system MORE INFORMATION ON OUR WEBSITE www smart e tech de slsc Copyrights SET GmbH All rights reserved Information contained herein is the property of SET GmbH and shall not be duplicated copied used or disclosed in wh...

Page 2: ...ding LVDT9312 Drivers To The Project Via Drag And Drop Function 15 3 4 1 6 Adding LVDT9312 Modules To The Project Via The Discovery Function 16 3 4 1 7 Adding FPGA Example Applications 17 3 4 1 8 Compiling And Running The Example Application 19 3 5 Using The Driver Together With A NI RealTime CompactRIO 20 3 5 1 1 Compiling And Running The Example Application 23 4 Connecting The LVDT Demodulator 2...

Page 3: ...cription Issue 05 24 05 2022 6 2 External Power Supply 36 6 3 Excitation Output 36 6 4 Ua and Ub Signal Inputs 37 6 5 Position Processing 37 6 6 Environmental Conditions 37 6 7 Connector Pinout 38 7 Module Calibration 38 8 Module Maintenance 38 9 Service Address 38 ...

Page 4: ...he shipment LVDT9312 cRIO module CD ROM with driver software application examples and manual 1 2 SAFETY INSTRUCTIONS 1 2 1 MODULE FAILURE Do not install the LVDT9312 module into a cRIO chassis when the module is obviously damaged physical damage lose parts inside the module 1 2 2 IMPERMISSIBLE APPLICATIONS The module is designed for laboratory use Installing or operating the module in explosive or...

Page 5: ...supply range from 9V to 36V and provides galvanic isolation between the cRIO and the demodulator interface The module is useable within the NI cRIO real time environment and can also be plugged into a NI R series expansion chassis with PCI PXI FPGA card We provide all drivers required for the cRIO system and LabVIEW integration examples LVDT9312 applications include industrial and military positio...

Page 6: ...driver software must be installed To do this use the LVDT9312 CD ROM and follow instructions To start the installation process execute the setup exe program on the CD ROM Please follow the instructions of the setup program to complete the driver installation When the installation is completed successfully the host system is ready to use LVDT9312 modules in a LabVIEW project ...

Page 7: ...cate with the LabVIEW application The FIFO buffers are organized in CommandIN FIFOs and CommandOUT FIFOs for bidirectional data flow from the application to the module and vice versa Note that these buffers are pre defined in the example project in terms of name and size and must not be modified to ensure correct operation see 3 4 1 4 Each driver VI uses two command FIFOs The user interface is for...

Page 8: ... LVDTCMD ctl For driver internal use CALLSTATES ctl For driver internal use FPGASTATES ctl For driver internal use The example project already covers all module slots with the maximum number of modules which is four when an R Series Expansion Chassis is applied and up to eight modules for a cRIO Chassis The names of the modules in the project and the correlating modules I O channels are pre define...

Page 9: ...rate the driver VI application Tree example programmes for the R Series Expansion Chassis and cRIO Chassis SET_LVDT_9312_Example_Slot_1 vi Program example which demonstrates the application of a single LVDT9312 module connected to slot 1 of a PCI FPGA R Series Expansion Chassis or a cRIO Chassis SET_LVDT_9312_Example_Slot_1 4 vi Program example which demonstrates the application of four LVDT9312 m...

Page 10: ... an R Series Expansion Chassis 3 4 1 1 CREATION OF A NEW PROJECT Copy all example project files included in LabVIEW on your local disk We recommend to copy the complete Folder in your LabVIEW project stricter To integrate the driver into an new LabVIEW project the target project must be opened subsequently Alternatively to start a new project File New Project must be clicked Opening the target pro...

Page 11: ...ect windows can be aligned as shown below The driver components can be copied into a new project via drag and drop function Note that the STRG key must be pressed during drag and drop to copy the element Otherwise the element will be removed from the example project The driver components can be copied by use of the drag and drop function ...

Page 12: ...scription Issue 05 24 05 2022 To add a new FPGA Target use the mouse and click right button onto the my computer symbol and select New Targets and Devices Select an existing FPGA Target or define a new device The new FGPA Target is now added to the project structure ...

Page 13: ...st be added to the actual project structure Use the mouse and click with the right button onto the newly added FPGA Target and select New R Series Expansion Chassis Confirm the dialog with OK The newly added R Series Expansion Chassis is now included in the project structure 3 4 1 4 ADDING THE LVDT9312 DRIVER COMPONENTS TO A PROJECT To include the driver components to the new project the files mus...

Page 14: ...14 of 38 www smart e tech com cRIO LVDT 9312 Module Technical Description Issue 05 24 05 2022 Copying the Driver Components via Drag n Drop ...

Page 15: ... already defined within the example project they can be copied with the drag and drop function Components which are not used in the new application can be removed from the new project Caution It is importent to Name the Modules Mod1 and not Chassis1 Mod1 like the default naming of the Discovery Function suggests Do not erase the contents of the libraries SET_SPI_Drivers lvlib and SET_LVDT_9312_Fun...

Page 16: ...les When the search procedure is complete LabVIEW adds an module item for each detected module and a virtual folder including the module IOs Automatik Detektion with wrong name for Module It is important that the I O names of the Module match the names expected by the driver Normally the correct I O name are created by LabVIEW within the discovery function However on some LabVIEW versions the I O ...

Page 17: ... Issue 05 24 05 2022 Renamed Module with copied Module Channels IOs 3 4 1 7 ADDING FPGA EXAMPLE APPLICATIONS To illustrate the driver use small example programs are provided with the module on the CD Use the copy paste function to copy these examples into the new application ...

Page 18: ...18 of 38 www smart e tech com cRIO LVDT 9312 Module Technical Description Issue 05 24 05 2022 All driver components and the example application are now added to the new project ...

Page 19: ...le within the project structure to start the slot 1 single module application example Then click the run button Now the compilation process starts and may take up to 60 minutes Note that the number of modules used in the application has an impact on the compilation time as every module uses separate driver VIs function VIs and FIFOs Compilation time depends on the used PC Hard and Software ...

Page 20: ...FPGA Target When the cRIO chassis and FPGA target does not exist in the new application it must be installed as shown in chapter 3 4 1 2 select New Targets and Devices device type cRIO Realtime by clicking the button LabVIEW now detects the connected cRIO chassis On detection of the chassis it must be selected and OK must be checked LabVIEW then asks for the I O acquisition mode Select method LabV...

Page 21: ...nical Description Issue 05 24 05 2022 On completion of the detection process LabVIEW adds the detected modules to the project structure as illustrated below Additionally a virtual I O folder for every new module is automatically installed within the project ...

Page 22: ...w smart e tech com cRIO LVDT 9312 Module Technical Description Issue 05 24 05 2022 Now the virtual folder Driver Components must be copied from the example project to the new FPGA target within the LabVIEW project ...

Page 23: ...tart the slot 1 single module application example Then click the run button Note This example is designed for an LVDT9312 Module in Slot 1 However it is easy to alter the example to work for a different slot Now the compilation process starts and may take up to 60 minutes Note that the number of modules used in the application has an impact on the compilation time as each module uses separate driv...

Page 24: ...t the module external power supply 9VDC 36VDC as shown below Connect the LVDT interface as shown below see also paragraph 6 7 Connector Pinout Connecting a 6 Wire LVDT LVDT9312 9V 36V Power Supply 9 36V Reg Excitation 2 COM 4 Ua HI 5 Ua LO 7 Ub HI 8 Ub LO 10 EXC HI 11 EXC LO 1 VS UP 6Wire LVDT Ub Ua Exc Connection a 6 Wire LVDT Connecting a 4 Wire LVDT LVDT9312 9V 36V Power Supply 9 36V Reg Excita...

Page 25: ...cation example can now be started by clicking the Run Button in LabVIEW Use parameters Amplitude mV and Frequency Hz to adjust the excitation signal to their correct levels After that specify the LVDT Type for the demodulation Stage The transfer Function for 6 Wire LVDT mode is 𝑃𝑜𝑠 𝑈𝑎 𝑈𝑏 𝑈𝑎 𝑈𝑏 The transfer Function for 4Wire LVDT mode is 𝑈𝑎 𝑒𝑥𝑐 the sign in 4W mode is determined by a separate phase...

Page 26: ...h the module and returns the response data to the calling process LVDT9312 Functions VI s The Functions VI provide the user interface for the application and transfer instructions and data to the driver VI These VIs act as clients for the transfer instructions and data to the driver VIs 5 1 1 1 DRIVER VI IMPLEMENTATION The implementation of the LVDT9312 drivers into a LabVIEW application takes pla...

Page 27: ...ach chassis slot requires a specific functions VI e g slot 1 slot 2 Calling a LVDT9312 function via the Functions VI When a Function VI is executed instructions and data are transferred to the corresponding FIFOs SlotN_CommandIN The applicable driver VI then communicates with the LVDT9312 module via the driver internal FIFO SlotN_CommandOUT Driver internal FIFOs for data transfer between Function ...

Page 28: ...it is essential to clear the FIFO contents during the programs initialisation sequence This is done by executing the Clear function after program start Important notice Execute the Clear instruction before any other VI call The example below illustrates the FIFO buffer clearing of an application which uses eight modules Clearing all used communication FIFOs during program start ...

Page 29: ... Function VI may be used within any LabVIEW structure like loops cases or sequences Furthermore multiple calls are allowed which are operated sequentially Note that the Function VIs use non re entrant structures Driver Call for Module in Slot 1 LVDT Function VI for Slot 1 Command DATA Slot1_CommandIN_FIFO The Function VI writes Command and DATA via Command_IN FIFO to the parallel running Driver VI...

Page 30: ... FIFO to the parallel running Driver VI Slot1_CommandOUT_FIFO The parallel running Driver VI stores the Answer Data in the Command_OUT FIFO Command ERROR DATA Calling LabVIEW Application SPI Driver VI for Slot 1 Driver VI for Slot 1 SPI Driver VI for Slot 2 Driver VI for Slot 2 SPI Driver VI for Slot N Driver VI for Slot N Driver Call for Module in Slot 2 LVDT Function VI for Slot 2 Command DATA S...

Page 31: ...g a timeout less than 40 000 000 has no effect because the default value cannot be reduced If an instruction takes longer than the specified timeout a fault is generated from the driver refer to the drivers fault codes Instruction U8 Tx Data U8 Receive Data I16 Data Sink Read Position 1 no data LVDT Position RAW LVDT Controller This instruction reads the actual LVDT position The data scaling is bi...

Page 32: ...at is a 16bit engineering value with dimension mVRMS This value is NOT for Position calculation and updated only 9 times per Second Instruction U8 Tx Data U8 Receive Data U16 Data Sink Read Channel B 7 no data Ch B Voltage mVRMS LVDT Controller This instruction reads input channel B voltage amplitude The return data format is a 16bit engineering value with dimension mVRMS This value is NOT for Pos...

Page 33: ... Valid Frequency Range 1000 Hz 10000 Hz Instruction U8 Tx Data U8 Receive Data U16 Data Sink Set LVDT Type 8 Res Mode Res Mode LVDT Controller This instruction programs the demodulation stage The data format is enumeration according to the following table Valid position resolution data Data 0 6 Wire LVDT demodulation Data 1 4 Wire LVDT demodulation Instruction U8 Tx Data U8 Receive Data U16 Data S...

Page 34: ... instruction is sent to the module while the module still processes a previous instruction and therefore the busy line still is active the FPGA driver waits for the busy line to return to the ready state The maximum idle time for the FPGA driver is a default value and can be increased from the user When the specified timeout is exceeded the error Module Busy is generated by the functions VI 103 Tr...

Page 35: ...2022 even if the external Supply is not applied 5 5 SAVING THE SETUP The LVDT9312 automatically saves the setup Excitation Amplitude Excitation Frequency and LVDT demodulation mode in a non volatile memory After a power cycle the last set Parameters are active when the Module is switched on ...

Page 36: ...er supply input is isolated from the cRIO chassis signals with a maximum isolation voltage of 500VDC Note that the excitation output and the Signals Ua and Ub are galvanically connected to the external power supply 6 3 EXCITATION OUTPUT Frequency 1kHz 10kHz adjustable via software Amplitude 2VRMS 7 VRMS adjustable via software Current max 120mARMS Caution The excitation output can be damaged when ...

Page 37: ...ded 27 5kOhm Caution The signal inputs can be damaged when the input voltage exceeds a limit of 40Vpeak 6 5 POSITION PROCESSING Resolution 16Bit Bandwidth Excitation Frequency Accuracy 0 1 accuracy of the module the Position accuracy depends on the xVDT the wiring and the Position of the xVDT 6 6 ENVIRONMENTAL CONDITIONS Temperature Range 0 C 70 C Humidity 10 90 relative non condensing ...

Page 38: ...B 9 GND 10 EXC 11 EXC 12 25 n c 7 MODULE CALIBRATION The LVDT9312 is calibrated when shipped A recalibration can be done by SET GmbH 8 MODULE MAINTENANCE No maintenance is required for the LVDT Module 9 SERVICE ADDRESS For technical support contact the SET service address SET GmbH August Braun Str 1 88239 Wangen Allgäu Germany Tel 49 0 7522 91687 600 Fax 49 0 7522 91687 899 e Mail support crio sma...

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