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PLL DATA OUT CIRCUIT
The VB7C chassis uses a new BUS-Controlled UHF/VHF Tuner with a built-
in Phase Locked Loop, Prescaler and Band Switch. Including these circuits
in the tuner reduced RF radiation and simplified shielding requirements and
printed wiring board layout. The primary difference between this chassis and
the previous chassis (C-983) is the exclusive PLL control lines (PLL Enable,
PLL Data, PLL Clock) are unified to the common BUS control lines (BUS SDA,
BUS SCL), and the BUS control program is incorporated in the CPU (C-003).
Channel selection requires only two inputs from the CPU. These are the Data
signal input from pin 32, and the Clock signal input from pin 34. The Data
signal controls the band switching, the channel selection and the AFT. The
channel selection and the AFT function are controlled by changing the divide
ratio for the PLL.
The tuning data format is composed of 5 byte data. See Tuning Data Format
figure below.
PLL Data Circuit
IC801
CPU
A101
TUNER
DATA
CLOCK
BUS
SDA
BUS
SCL
32
34
R856
R881
R882
R857
L881
L882
