Sanyo AVM-2550S, AVM-2759S Training Manual Download Page 20

Page: 20 / 75

– 17 –

IC Write Address: 84h (10000100)

Sub Address

(MSB)

DATA

(LSB)

• • • • • •

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

00h

✻

TEST-DA

TEST 1

ATT (Note-1)

01h

✻

SPECTRAL (Note-2)

02h

✻

WIDEBAND (Note-2)

03h

✻

EXT1

EXT2

NRSW

FOMO

SAPC

(Note-5)

(Note-3)

(Note-4)

(Note-5)

04h

✻

PSW

✻

SURR

ATT SW

✻

FEXT1

FEXT2

(Note-6)

05h

✻

BASS (Note-7)

06h

✻

TREBLE (Note-7)

07h

✻

VOL-L (Note-8)

08h

✻

VOL-R (Note-8)

•

Note-1: ATT for the Input Level Adjustment.

•

Note-2: SPECTRAL for the High Separation and WIDEBAND for Low Separation

Adjustments.

•

Note-3: EXT1 and EXT2 for the AV Selection.

•

Note-4: NRSW for Stereo/SAP Selection and FOMO for Forced Mono Selection.

Mode

EXT1

EXT2

AV1

AV2

Mode selected Receiving Signal

NRSW

FOMO

Output Signal

MONO

Mono

✻

MONO

Stereo

MONO

SAP + Mono

MONO

SAP + Stereo

MONO

STEREO

Mono

MONO

Stereo

STEREO

SAP + Mono

MONO

SAP + Stereo

STEREO

SAP

Mono

MONO

Stereo

STEREO

SAP + Mono

SAP

SAP + Stereo

SAP

•

Note-5: M1 for TVOUT Mute and M2 for LSOUT Mute functions. LSOUT Mute is

accomplished by M2 and Volume Mute.

Mode

Data

MUTE ON

MUTE OFF

•

Note-6: SURR for Surround On/Off Selection.

Mode

Data

SURROUND OFF

SURROUND ON

•

Note-7: BASS for Bass Control and TREBLE for Treble Control.

Control Level

Data

MAXIMUM

3Fh (111111b)

CENTER

1Fh (011111b)

MINIMUM

00h (000000b)

•

Note-8: VOL-L for L-Channel Volume Control and VOL-R for R-Channel Volume

Control.

IC Read Address: 85h (10000101)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POWER STEREO

SAP

NOISE

––

✻

: Don’t care bit.

POWER=1 : Reset
STEREO=1 : Stereo is present.
STEREO=0 : Stereo is absent.
SAP=1, NOISE=0 : SAP is present.
SAP=1, NOISE=1 : SAP is absent.
SAP=0 : SAP is absent.

Summary of Contents for AVM-2550S, AVM-2759S

Page 1: ...SANYO FISHER SERVICE CORPORATION TRAINING MANUAL AS REFERENCE No TI780010 INTRODUCTION TO THE VB7C CHASSIS AVM 2780G AS FGH ...

Page 2: ...TV Repair Membership Site Plasma 3D TV Repair Membership Site Projection TV DLP LCD Projector Repair Membership Site Troubleshooting Repairing LCD TV Guide Plasma TV Repair Guide Display Fault Troubleshooting Basic LCD TV Repair Secrets Revealed LCD Monitor Repair Guide Vol 1 10 Trus Repair Case Histories of LCD Monitor SMPS Switch Mode Power Supply Repair Guide Testing Electronic Components like ...

Page 3: ...mation about parts CPU programming safety and alignment procedures Safety Information All product safety requirements and testing must be completed prior to returning the television to the consumer Do not defeat safety features or fail to perform safety checks Failure to comply with these safety procedures may result in damage or personal injury Integrated circuits and many other semiconductors ar...

Page 4: ...CIRCUITS 24 REFERENCE OSCILLATOR 26 CRT DISPLAY CIRCUIT 27 MEMORY CONTROL CIRCUIT 28 MOMENTARY MUTE CIRCUIT 30 AFT DEFEAT CIRCUIT 32 CPU RESET OPERATION 34 AUTOMATIC BRIGHT LEVEL ADJUSTMENT SYSTEM 36 AUTOMATIC RF AGC ADJUSTMENT SYSTEM 40 CLOSED CAPTIONING DESCRIPTION 44 THE CLOSED CAPTION DECODER SECTION 46 CAPTION DATA SLICER 48 F S TUNING SYSTEM DESCRIPTION 52 PLL OPERATION 54 PIP CONTROL CIRCUI...

Page 5: ...p function PLL programmable divider and phase detector 7 Power supply protection function 8 Digital control functions for picture and audio 9 Trilingual English Spanish French On Screen menu system 10 AFT search function 11 Caption Data Slicer 12 V Guide control function 13 Color Enhancer control function 14 On screen Service Adjustment Menu system 15 Automatic RF AGC adjustment system 16 Automati...

Page 6: ...ock Diagram TUNER EEPROM KEY BOARD RC PRE AMP DISPLAY DIGICON SOUND AV MTS PIP AFT CAPTION DATA SLICER OSD CPU C 003 COMPOSITE VIDEO RF AGC A D INPUT BUS CONTROLLED SIGNAL PROCESSOR BEAM CURRENT DETECTOR PLL PRE SCALER BAND SW ...

Page 7: ... the option data in IC802 the EEPROM The Service Adjustment Menu display shown below and the following table show the different options available and the necessary data The option data shown are for Mode AVM 2780G and include these options with Clock with Surround with Software for PIP Rating Information Processing with Color Enhancer with Initial Channel with PIP with 2 AV Inputs and with Bass Tr...

Page 8: ...complete adjustment procedure When the Initial Channel option is used the Initial Channel the TV can be set automatically to tune to a specific channel each time it is turned on and XDS Extended Data Service features are available BIT FUNCTION DATA 0 1 0 NOT USED 1 NOT USED 2 NOT USED 00 NONE 3 4 CLOCK 01 YES AC 60 Hz 10 YES INT OSC 11 INHIBITED NONE 5 NOT USED 6 SURROUND NONE YES 7 NOT USED BIT F...

Page 9: ... and those of the remote control transmitter are the same The following keys when activated perform a series step action The time of each series step action is also shown below A CH Up Down 500 ms step B Vol Up Down 140ms step It takes about 9 seconds to change from minimum to maximum volume Preceding and succeeding mutes are performed when turning power Off On changing channels switching Antenna ...

Page 10: ... 7 9 ALWAYS 5V SW1901 POWER SW1902 VOL SW1903 VOL SW1904 CH SW1906 MENU R1907 R1906 R1905 R1904 R1903 R1902 R1901 C1902 L1901 R1910 IC801 CPU SW1905 CH D1901 7 5V Key Scan Circuit ...

Page 11: ...n the normal mode and then inverted This provides a type of redundancy check to prevent misoperation Custom and Data codes differentiate between the 1 and 9 values by the pulse duration See 1 and 0 Pulse Duration diagram below The custom code is a unique code assigned to each manufacturer Its purpose is to help prevent operation of the TV by remote controls for other components such as VCRs CD pla...

Page 12: ...ation Custom Code LEADER CODE CUSTOM CODE CUSTOM CODE DATA CODE DATA CODE 27ms 9ms 4 5ms 27ms C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 1 125ms 2 25ms 1 125ms 2 25ms 0 1 0 1 0 56ms ms 0 1 LEADER CODE DATA CODE 1 0 0 1 1 1 0 0 1 1 1 0 0 0 ...

Page 13: ...nified to the common BUS control lines BUS SDA BUS SCL and the BUS control program is incorporated in the CPU C 003 Channel selection requires only two inputs from the CPU These are the Data signal input from pin 32 and the Clock signal input from pin 34 The Data signal controls the band switching the channel selection and the AFT The channel selection and the AFT function are controlled by changi...

Page 14: ...A acknowledge MA1 and MA2 address selection bits M8 M0 S4 S0 programmable divider bits CP charge pump current tuning speed switch control T1 test mode selection CD charge pump defeat switch control X don t care bit BU UHF band switch control FMT FM trap 92 5MHz switch control at channel 6 BVH VH band switch control BVL VL band switch control BAND BU FMT BVH BVL VL WITHOUT CH 06 ONLY L L L H VL CH ...

Page 15: ...e signal at pin 29 is between 3 3 VDC and 1 67 VDC However the slope right down is also checked to distinguish the station center from a pseudo tuning point The Time Base signal is the AND signal of the horizontal sync signal from the flyback transformer and the horizontal sync signal from the video Y signal The AFT S Curve signal is an indication of the video IF carrier frequency 45 75 MHz The Ti...

Page 16: ... 13 RANGE OF 0 5 V AFT S Curve Signal 3 3 V 1 67 V TUNING POINT AFT S CURVE Station Center Time Base Signal CPU TIME BASE SIGNAL ...

Page 17: ...sed accuracy of the factory adjustments during production This is due to the computerized and digitized control circuit which allows remote operation Control of the Signal Processor IC is through CPU pins 32 and 34 Pin 34 is the BUS SCL Serial Data signal The BUS SDA is a bi directional signal and is used to transfer data into and out of the control registers within IC101 Data is processed through...

Page 18: ...ntrol 7 Customer color control White Peak Limiter Enable 1 Disable White Peak Limiter G Drive Reduction 4 Select Green OUT AC level V Size Compensation 3 Selected Gain of V Size Compensation Video Level 3 Align IF video level FM Level 5 Align WBA output level Audio SW 1 Select Audio Signal INT EXT Volume Control 7 Customer volume control Control Register Descriptions IC Address BAh 10111010 Sub Ad...

Page 19: ...oduction This is due to the computerized and digitized control circuit which allows remote operation Control of the MTS Processor IC is through CPU pins 32 and 34 Pin 34 is the BUS SCL Serial Clock signal The BUS SCL input is used to clock all data into and out of IC101 Pin 32 is the BUS SDA Serial Data signal The BUS SDA is a bi directional signal and is used to transfer data into and out of the ...

Page 20: ...o 0 MONO Stereo 0 1 MONO SAP Mono 0 1 MONO SAP Stereo 0 1 MONO STEREO Mono 0 1 MONO Stereo 0 0 STEREO SAP Mono 0 1 MONO SAP Stereo 0 0 STEREO SAP Mono 0 1 MONO Stereo 0 0 STEREO SAP Mono 1 0 SAP SAP Stereo 1 0 SAP Note 5 M1 for TVOUT Mute and M2 for LSOUT Mute functions LSOUT Mute is accomplished by M2 and Volume Mute Mode Data MUTE ON 0 MUTE OFF 1 Note 6 SURR for Surround On Off Selection Mode Da...

Page 21: ...the Audio Mute Control Register M2 Sub Address 03h Bit 6 respectively to set the output sound level to step 0 63 during Mute ON See page 30 for the Audio Mute Control Register M2 In addition the CPU outputs the Mute High signal from pin 38 to prevent buzz or static in the speakers when turning On Off or during Standby mode The Mute High is coupled to the base of Q001 switching Q001 On grounding pi...

Page 22: ...V2 R 13 MTS DECODER BLOCK AUDIO SW 39 C002 L R C001 3 1 C011 SP901 SPEAKER R SP902 SPEAKER L C3437 L R C3435 R L K1011 FIXED AUDIO OUT R K1021 FIXED AUDIO OUT L to BUS Line 32 34 IC3401 MTS PROCESSOR VOLUME CONTROL BASS TREBLE CONTROL SURROUND BLOCK VOL R VOL L BASS TREBLE SURR M2 EXT1 EXT2 M1 33 34 36 37 FEXT1 FEXT2 MUTE 38 5 C007 R011 Q001 MOMENTARY MUTE R012 ...

Page 23: ...econds to change from center to minimum or center to maximum The BUS data changes for the controls are the same as those shown for the volume control When the FACTORY PRESET mode is selected with the RESET key the Picture Sound controls will return to the factory settings During FACTORY PRESET mode the settings are as follows COLOR 32 64 1 TINT 32 64 1 CONTRAST 64 64 2 BRIGHTNESS 32 64 3 SHARPNESS...

Page 24: ... L OUT IC801 CPU Write 5 bit Write 7 bit Write 7 bit Write 7 bit Write 6 6 bit Write 6 bit Write 6 bit FUNCTION BTS OUTPUT RANGE OF BUS DATA RANGE OF STEPS CUSTOMER CONTROL SERVICE ADJUSTMENT Color 7 0 127 0 64 127x1 5 0 127 96 127 0 31 127 0 127 31 127 Tint 7 0 127 0 64 127x1 5 0 127 96 127 0 31 127 0 127 31 127 Contrast 7 31 127 0 64 127x1 5 31 127 31 127 127 127 0 127 0 127 Brightness 7 0 127 0...

Page 25: ...d every 20 ms Note The C 003 CPU provides a Power Surge Protection feature If power failures occur three times within 15 minutes the CPU will automatically stop functioning to help prevent secondary damage TV will not turn On by pressing the POWER key To reset the operating programs within the CPU disconnect the AC power cord for at least 10 seconds Auto Shut Off Function The Auto Shut Off feature...

Page 26: ...R ON OFF POWER FAIL R629 D629 20V D680 R628 R627 R691 Q627 B4 12V L623 D624 T601 POWER D683 TJ2 RL601 PS601 POSISTOR L901 DEGAUSSING COIL R835 7 6V D801 TJ7 R498 C497 C258 D493 7 5V R310 4 8V TJ5 Q486 9V R486 R487 D486 10V D312 R311 D311 5V D489 C484 D429 R428 D428 15V D482 R482 R497 7V IC801 CPU C629 C626 R489 IC681 5V REG ...

Page 27: ...AV1 Composite Video or AV2 Video signal is controlled by the CPU and the mechanical switch of AV1 S Video input jack K1051 When the AV1 is selected pin 5 of the CPU will be Low When the AV2 is selected pin 5 of the CPU will go High When the AV1 S Video is connected during AV1 mode pin 10 of IC1001 and pin 12 of the CPU will be forced Low With the Low at pin 12 the CPU will regard the S Video as co...

Page 28: ...AUDIO L AV2 AUDIO L AV1 AUDIO R AV2 AUDIO R IC001 AUDIO AMP IC8001 PIP SIGNAL PROCESSOR 34 36 37 33 IC3401 MTS PROCESSOR 5 6 38 39 3 4 13 23 ACK Q8097 BUFFER Q8093 BUFFER Q8090 BUFFER Q8076 BUFFER SDA SCL INPUT FILTER Q8073 BUFF BUS SCL 34 MUTE 38 TV AV 8 BUS SDA 32 IC801 CPU S1 SW 12 MAIN AV1 AV2 5 PIP TV AV 7 PIP AV1 AV2 6 MAIN S SELECT 4 A101 TUNER 9V 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 H L ...

Page 29: ...e clock signal TIME DISPLAY FEATURE The C 003 CPU provides a time display feature The time of day clock is timed by counting the reference oscillator frequency of 8 MHz served to the CPU The oscillator frequency is maintained accurate within 0 003 percent which provides a convenient and accurate timing signal for the clock The Clock and the Sleep Timer cannot be set if this timing signal is missin...

Page 30: ...d number of clock pulses the letter signals are output on pins 40 42 and the blanking signals are output on pin 39 The letter and the blanking signals are output as active Highs The exact count of horizontal sync pulses and 8 MHz clock pulses is controlled by the CPU program and will change with the display pattern All display signals from the CPU are input to IC101 the Signal Processor on pins 33...

Page 31: ...Off mode Color Enhancer mode the Line SW On Off mode and the BUS data used for factory service adjustments The Line SW On Off mode is a special mode used only for production Control of the memory IC is through CPU pins 31 and 33 Pin 33 is the IIC SCL Serial Clock signal The IIC SCL input is used to clock all data into and out of IC802 Pin 31 is the IIC SDA Serial Data signal The IIC SDA is a bidir...

Page 32: ... O P P NOTE ACK ACKNOWLEDGE BIT Write In Mode S 1 1 0 0 1 0 0 0 0 P Read Out Mode CPU CPU CPU CPU A C K A C K A C K A C K CONTROL BYTE READ WRITE NOTE ACK ACKNOWLEDGE BIT DEVICE CODE S T A R T A C K S T O P A C K DATA n DATA n X S 1 1 0 0 0 0 0 0 0 S T A R T DEVICE CODE CONTROL BYTE A C K READ WRITE WORD ADDRESS n A C K ...

Page 33: ... bit data 0 into each of the Audio Mute Control Registers to minimize the output level at pins 3 4 38 and 39 of IC3401 In addition the Mute High is coupled to the base of Q001 switching Q001 On grounding pin 5 of IC001 The minimum output level at pins 3 4 38 and 39 of IC3401 and the Low at pin 5 of IC001 will mute the audio output of the Audio Amplifier IC001 and the external audio equipment preve...

Page 34: ...V2 R 13 MTS DECODER BLOCK AUDIO SW 39 C002 L R C001 3 1 C011 SP901 SPEAKER R SP902 SPEAKER L C3437 L R C3435 R L K1011 FIXED AUDIO OUT R K1021 FIXED AUDIO OUT L to BUS Line 32 34 IC3401 MTS PROCESSOR VOLUME CONTROL BASS TREBLE CONTROL SURROUND BLOCK VOL R VOL L BASS TREBLE SURR M2 EXT1 EXT2 M1 33 34 36 37 FEXT1 FEXT2 MUTE 38 5 C007 R011 Q001 MOMENTARY MUTE R012 ...

Page 35: ... voltage at pin 13 of IC101 will be fixed to 1 2Vcc approx 3 8VDC When changing channels the AFT enabling BUS data is input to the BUS Interface circuit to write a 1 bit data 0 into the AFT Defeat Control Register allowing the AFT circuit to operate An additional adjustment mode is provided for the service adjustment to disable the AFT Circuitry continuously for adjusting the APC DET and PLL Tunin...

Page 36: ...Audio SW 5 3 2 LIM AMP Write 5 bit FM Level FM AMP 7 50 3 8V Multiplier 52 49 CLAMP 45 47 Video SW 1 42 4 R167 C161 R162 R168 R161 AFT Out 29 AFT S Curve C142 PIF AGC Filter C151 R151 PIF APC Filter BUS GND N C Vol Filter N C Audio Out N C EXT Audio In T151 VCO Tank FM Filter C131 FM Out TP21 T131 FM Coil R133 C133 R207 Selected Video Out C147 VIF VCC R159 R163 R169 X153 4 5MHz BPF X161 L164 TP16 ...

Page 37: ... will be set to the last Language selected M The Color Enhancer mode will be set to the last Color Enhancer mode NORMAL or WARM selected The reset operation provides two functions for the CPU system First when power is first applied to the system the reset circuit will initiate a micro computer program within the CPU This sets the CPU into the conditions described above Second at the time of a pow...

Page 38: ...PU C811 25 RESET AVCC CPU Reset Circuit 22 VCC L851 L821 ALWAYS 5V D831 3 6V R816 R814 Q831 R813 C822 C806 4 5 V 2µS 15µS CPU Reset Voltage 4 V CPU VCC 22 CPU AVCC 14 CPU RESET 25 CPU RESET 25 CPU VCC 22 CPU AVCC 14 ...

Page 39: ...evel adjustment system is composed of the beam current detection circuit and the automatic adjustment program in the CPU The fundamental operations are described below Fundamental Operation The BUS data for the brightness control with the 7 bit control data up to 127 steps is output from IC801 the CPU The 64 steps are used for customer control and the remainder 63 steps are provided for bright lev...

Page 40: ...on Circuit B 130V C829 R831 D834 18V D836 R833 R494 R493 R491 R492 D487 C493 HV Brightness Control Register IC101 Signal Processor BUS Data Special Signal Input A D Input Voltage AVERAGE BEAM CURRENT µ A Vcc A D Input Voltage at 0 beam current Suggested Beam Current for 12 IRE flat video signal input during FACTORY PRESET mode 0 100 200 5 steps 20 128 Vcc A D INPUT VOLTAGE Vcc 5V 53 128 Vcc 49 128...

Page 41: ...tage is input to pin 30 A D input of the CPU When the maximum A D input voltage at pin 30 is between 21 128 Vcc 0 82V and Vcc 5 0V the specified video signal is determined to have been input and the A D input voltage is read by the 5 bit 31 steps comparator The CPU will begin decreasing the reference voltage from 125 128 Vcc 31 31 steps sown to 21 128 Vcc 5 31 steps by 2steps 8 128 Vcc until the r...

Page 42: ...US Data Outputs for AUTO mode BRIGHTNESS 50 127 3 CONTRAST 64 64 Read A D Input Voltage at CPU pin 30 A D Input Voltage 4 A 20 128Vcc Increase 1 step 1 63 of BUS Data Output for Bright Level Adjustment Memorize Bright Level Exit Automatic Adjustment mode Error YES NO YES YES NO NO Enter Automatic Adjustment mode Error Wait for 100 msec Wait for 1 sec Wait for 200 msec Wait for 70 msec 2 range is b...

Page 43: ...ed of the RF AGC A D Analog Digital input circuit the automatic adjustment program in the CPU and the Signal Processor The fundamental operations are described below Fundamental Operation The BUS data for the RF AGC Delay control with the 6 bit control data up to 64 steps is output from IC801 the CPU The BUS data for the RF AGC control is coupled to the BUS Interface circuit within IC101 the Signa...

Page 44: ...INPUT VOLTAGE Vcc 5V RF AGC A D Input Voltage 79 128 Vcc DOMAIN OF DISTORTION DOMAIN OF NOISE Video Amp A101 Tuner Video Chroma Processing Circuit AVM 2780G Automatic RF AGC Adjustment System CRT DC Level Audio Processing Circuit Speaker Video Detector VIF Amp IF AGC RF AGC Amp X141 SAW AGC IF VIF SIF Processing Circuit 2nd AGC Fiter IF AGC Drive BUS Interface Write 6 bit IC101 Signal Processor RF...

Page 45: ...hat a stable RF AGC voltage can be read When the A D input voltage is between 69 128 Vcc 2 70V and 85 128 Vcc 3 32V the RF AGC adjustment is determined to have been normally completed and the BUS data in the RF AGC Delay Control Register is memorized into IC802 the Memory IC If when the A D input voltage is read the A D input voltage is higher than 85 128 Vcc 3 32V the CPU will begin increasing th...

Page 46: ... RF AGC Delay Control BUS Data 0 steps Write Automatic RF AGC Adjustment Result NG into Memory IC Write Automatic RF AGC Adjustment Result OK into Memory IC Preset BUS Data for RF AGC Delay Control to 011001 25 64 steps Write Automatic RF AGC Adjustment Data into Memory IC Add 1 step 1 64 from BUS Data for RF AGC Delay Control BUS Data 64 step Output BUS Data for RF AGC Delay Control Exit Automati...

Page 47: ...ear at once In the paint on mode the characters are displayed as they are received one column at a time from left to right Text Text is non video related information and is displayed in a black box which overwrites the screen In a full screen Text mode the box is 15 rows high and 34 columns wide The rows may contain a maximum of 32 characters When all 15 rows have been used the display scrolls up ...

Page 48: ... 45 Line 21 Field 1 Encoded Composite Data Signal D1 D7 D1 P D7 P H sync Program Color Burst Character 1 Character 2 Start Bit Clock Run in 7 Cycles CLOCK PULSE in BURST Odd Field ...

Page 49: ...ets the digital data signal input from the Data Slicer through the Internal Bus Specifically the Data Slicer applies error detection and correction to the incoming data and evaluates the data for display format and character attributes The OSD then directs the operation of the Display RAM and Character ROM of the OSD In addition the OSD block controls the mode selection Caption Text C1 C2 etc base...

Page 50: ...r address 00D116 Block Control Register address 00D216 00D316 Vert Position Register address 00D416 00D516 Window Register address 00D616 00D716 I O Polarity Control Register address 00D816 Raster Color Register address 00D916 B output G output BOX output R output G R B OUT1 42 41 40 39 1 2 23 24 OSC N C Data Slicer DATA SLICER CLOCK 27MHz OSC1 OSC2 17 C854 R854 R853 C853 2 bytes x 32 characters x...

Page 51: ...NG GENERATOR The composite sync signal from the Sync Slicer is input to the Sync Separator and separated into the horizontal sync signal Hsep and the vertical sync signal Vsep The Timing Signal Generator controlled by the Data Slicer Control Registers 1 2 generates a reference clock signal with a clock rate of 13 0832MHz 832fH The clock signal the separated horizontal sync signal and the separated...

Page 52: ...nal Generator Data Slicer Interrupt Signal Sync Pulse Counter Register Data Slicer Control Register 2 Caption Position Register Data Clock Position Register 15 1 17 16 C853 R853 R854 C854 C856 R851 C857 HLF HSYNC CVIN VHOLD C858 Comparator IC801 CPU C 003 Data Slicer ON OFF INTERNAL BUS Clock Run In Detection Register Data Slicer Control Register 1 Composite Video Signal Horizontal Sync Signal t C...

Page 53: ...The Start Bit Detector detects a start bit on Line 21 detected by the Line 21 Discriminator CLOCK RUN IN DISCRIMINATOR The Clock Run In discrimination is accomplished by counting the number of the output pulses from the Comparator in the window set up after the first pulse of the Clock Run In 16 BIT SHIFT REGISTER The output signal from the Comparator is stored in the 16 Bit Shift Register only wh...

Page 54: ... Vsep Hsep Vertical Interval Caption Data Line 21 Caption Data Enlarged Hsep Video Signal Clock Run In Start Bit 16 Data The presence of the Clock Run In is determined by the number 4 6 of Clock Run In pulses in the Window Window Data Slicer Timing Control Signal ...

Page 55: ...us and present system is shown below In operation the tuner is precisely adjusted to the frequency of the channel selected by phase comparing after frequency division the tuner local oscillator frequency with a crystal controlled oscillator reference frequency in the MIX OSC PLL IC CXA3135AN Any deviation of the local oscillator frequency from the correct channel frequency will result in an output...

Page 56: ...rammable divider bits N M8x213 S2x22 S1x2 S0 CP charge pump current tuning speed switch control T1 test mode selection CD charge pump defeat switch control X don t care bit BU UHF band switch control FMT FM trap 92 5MHz switch control at channel 6 See Table 2 BVH VH band switch control BVL VL band switch control BAND BU FMT BVH BVL VL WITHOUT CH 06 ONLY L L L H VL CH 06 ONLY L H L H VH L L H L UHF...

Page 57: ...ded local oscillator frequency is phase compared with the divided reference oscillator frequency by the phase comparator Any phase error will generate a correction voltage which is amplified and applied to the tuner local oscillator SUMMARY The PLL always phase compares the local oscillator frequency with the reference frequency If the local oscillator frequency deviates even slightly from the nor...

Page 58: ...ISTER PRESCALER 1 8 4 5 6 7 DECODER CPU TUNER CHARGE PUMP OUT BU BVH BVL LOCAL CXA3135AN MAIN COUNTER SWALLOW COUNTER 9 bit 5 bit PROGRAMMABLE DIVIDER 4 bit 14 bit ADSW SDA SCL 7 8125 KHz 4 MHz 7 8125 KHz REF OSC 4 MHz CRYSTAL Synthesizer Tuning Circuit LOCK DET BAND SW DRIVER UHF VHF LOCAL OSC BUFFER 26 LOCK FMT ...

Page 59: ...nput output from pin 32 and the SCL Serial Clock input from pin 34 The Data signals control the PIP On Off the PIP Swap PIP Location PIP Freeze and PIP Select functions When the power is switched On the 12 VDC and PIP 3 3 VDC supply lines will gradually rise At 60ms after pin 27 of the CPU goes High IC8001 will execute a Power On Reset initializing all internal registers to 0 zero and resetting th...

Page 60: ...NC MAIN PIX V SYNC 5 7 T402 IC501 IC8001 PIP SIGNAL PROCESSOR PIP Control Circuits R8006 9V R8036 C8036 SCL SDA POWER ON RESET 3 3V L8094 L8098 H PULSE V PULSE ALWAYS 5V R821 R826 L8008 Q8006 R8003 R8005 L8007 Q8005 L8036 C8003 R8095 R8088 Q8097 R8096 23 ACK R8091 R8090 R8092 R8089 R8093 Q8090 Q8093 L8070 Q8000 R8002 R8001 R8009 D8000 3 9V C8072 3 3V ...

Page 61: ...put Switch The PIP Signal Processor contains the sub picture signal processing circuit The built in field memory 96K bit RAM is necessary to provide for the data storage of a sub picture into the main picture of a television The sub picture processing circuit includes the A D Converter Y C Separator V Chip Data Slicer Timing Control Vertical Filter Multiplexer Field Memory Demultiplexer Encoder D ...

Page 62: ... SWITCH R1082 K1001 V1 IN Q1093 Q1094 Q1096 R1007 C1 C1 Y1 V1 R1042 C C Y R1081 C1 C COMB EXT V Y Y COMB Q332 BUFFER YC MIX V2 EXT V IN INT V FOR PIP 49 Sync tip Clamp 51 xx xx 25 23 13 14 40 39 37 38 8 24 9 15 10 Bias 15 3 I2C I F V chip data slicer Sync tip Clamp A D 8bit Y C SEP LPF BPF Phase Select HD D A 8bit D A 8bit Delay I2C HPLL 4fsc Delay Encode 4fsc MIX Level Detect Burst Data Sampling ...

Page 63: ... block The input signal then passes through the fixed de emphasis circuit and is applied to the variable de emphasis circuit The signal output from the variable de emphasis circuit passes through an external capacitor and is applied to VCA voltage control amplifier Finally the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix The variab...

Page 64: ...TRIX Lch Rch MODE CONTROL SAP IN 4 7µ SAP FM DET SAP LPF I2C BUS DECODER MODE CONTROL SAP BPF SAP OUT L R to TVSW NOISE DET I2C BUS DECODER SAP DET I2C BUS DECODER A B 13 9 8 21 22 24 25 Fig 2 Overall block diagram See Fig 3 for the dbx TV block NR SW FIXED DEEMPHASIS VARIABLE DEEMPHASIS VE OUT VCA IN to MATRIX 4 7µ HPF LPF LPF RMS DET RMS DET VCA A B ST IN SAP IN 22 25 29 30 Fig 3 dbx TV block Lc...

Page 65: ...in the addition or the subtraction of the BUS data for the R Drive or B Drive control was out of the range of the Control Register the data is limited to 0 step 0 127 or 127step 127 127 When the Color Enhancer mode is Warm and during the larger amplitude of white signal in brighter scenes the white balance will become reddish This operation is accomplished by decreasing the amplitude white simulta...

Page 66: ...e video signal The center frequency is fsc 5 Dynamic Comb Filter DCF This block is logical comb filter to extract the chrominance signal Filtering logic applies a correlation of two lines to reduce color dot crawl and cross color 6 Color Killer Circuit Killer This block is applied for black and white B W signals which have no color burst When pin 10 Killer is H logic stops Y C separation and outpu...

Page 67: ...ng circuit to produce oscillation by turning the switching transistor Q601 On and Off Therefore we need to examine each state Off Operation Off Period On Operation and On Period of the switching transistor separately l Off operation When control circuit is not operating Because the feedback voltage is determined by the turn ratio of input coil to feedback coil it is constant when the DC input volt...

Page 68: ...D612 R630 TJ1 TJ2 TJ6 R621 C622 L621 D624 C625 D625 L625 L628 R695 C628 C626 IC801 CPU B4 12V B1 130V 16V RL601 D683 KD A1 A2 PS601 5 6V 27 12 1 2 4 3 2 3 14 5 6 7 8 11 15 16 L601 13 POWER R618 B4 12V C620 L623 1 2 3 IC601 C630 Q695 R694 Q693 D693 6 2V C693 R693 R692 Q635 R631 R634 R632 C634 A R691 R627 R628 Q627 Q681 R629 D680 D629 16V C629 C481 C683 R683 POWER ON OFF 1 2 3 ALWAYS 5V IC681 D694 D...

Page 69: ...ollector the output from the photo diode inside D612 will also increase The output of this photo diode will be received by its photo transistor and the impedance between the collector and emitter of the transistor will decrease When the impedance decreases the current from the collector of the photo transistor will increase This will cause an increase in the collector current of Q605 and the base ...

Page 70: ... CURRENT POSITIVE FEEDBACK VOLTAGE OUTPUT VOLTAGE 0V 0A 0A 0V A Q601 COLLECTOR EMITTER VOLTAGE B T601 TERMINAL CURRENT C Q601 COLLECTOR CURRENT D T601 TERMINAL VOLTAGE E T601 TERMINAL CURRENT 0A F T601 TERMINAL VOLTAGE G Q604 BASE EMITTER VOLTAGE T1 T3 T2 I Q601 OFF PERIOD Q601 ON OPERATION Q601 ON PERIOD 0V 0V 0A ...

Page 71: ...er To suppress the surge voltage R604 R606 and C608 are provided R614 C612 and D609 During the On operation of Q601 D609 cannot be conductive if the positive feedback voltage is lower than 0 6V However during the lower positive feedback voltage the current goes through R614 and C612 and turns Q601 On After Q601 is On the base current will be supplied through D609 OVERLOAD PROTECTION CIRCUIT The po...

Page 72: ...On and Q605 and Q604 will turn On then the switching transistor Q601 will turn Off As a result the oscillation of the power supply circuits will stop and the output voltages of the power supply circuits will fall down Also the voltage at point A will gradually fall down from 12V When the voltage at the base of Q693 becomes lower than the triggering value 0 6 0 7V higher than emitter voltage of Q69...

Page 73: ... Check IC801 4 Check for a LOW to HIGH state change IC801 pin 27 with operation of the power key A If no change check all keys for stuck closed condition B Check remote operation C Check IC801 5 If pin 27 of IC801 changes from a LOW to a HIGH state check 12V Switch Drive Transistor Q681 and 12V Switch Transistor Q627 No Remote Operation Manual Operation OK 1 Check for 5 volts on pin 2 of RC Pre Am...

Page 74: ...1 pins 9 and 10 when connecting known S Video signal to S Video Input jack A If pins 9 10 do not switch correctly check IC801 and IC1081 Color Enhancer 1 With an oscilloscope check for R and B output signals on pins 28 and 30 of IC101 when selecting Warm mode A If pins 28 and 30 do not change check IC101 and IC801 No PIP Picture 1 Check PIP 3 3 volt power supply Q8000 emitter A If no 3 3 volt powe...

Page 75: ...TV AV MAIN TV VIDEO KEY SCAN IN REMOTE CONTROL IN N A Open S1 DETECT SW CVIN N A Open AVcc 5V X IN V HOLD IN Vss GND R G B BLK MUTE ACK STATUS S2 DEFEAT SW BUS SCL IIC SCL IIC SDA AFT S CURVE RF AGC POWER TIME BASE RESET N A Pull Down AC 50 60Hz Open Vcc 5V ABL IN CPU Pin Allotment HLF CNVss GND X OUT BUS SDA I I I O O O O O I I I O O O O O I I I O I O I I O I I I O O I O I O I I O I O I ...

Search results

Summary of Contents for AVM-2550S, AVM-2759S

Reviews:

Related manuals for AVM-2550S, AVM-2759S

Brands by name

Popular brands

Sanyo AVM-2550S, AVM-2759S, Training Manual

Search results

Summary of Contents for AVM-2550S, AVM-2759S

Reviews:

Related manuals for AVM-2550S, AVM-2759S

Brands by name

Popular brands